SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.21.1 GPMC_CONFIG3 Register (Offset = 68h) [reset = 22060514h]

ADV# signal timing parameter configuration

Offset = Base + (j * 30h); where j = 0 to 3d

Table 5-1208 Instance Table

Instance Name	Physical Address
GPMC0	4840 0068h + formula

Figure 5-599 GPMC_CONFIG3 Name Register

Table 5-1209 GPMC_CONFIG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED_1	R	0h	Write 0's for future compatibility. Read returns 0
30:28	ADVAADMUXWROFFTIME	R/W	2h	ADV# de-assertion for first address phase when using the AAD-Mux protocol
27	RESERVED_0	R	0h	Write 0's for future compatibility. Read returns 0
26:24	ADVAADMUXRDOFFTIME	R/W	2h	ADV# assertion for first address phase when using the AAD-Mux protocol
23:21	RESERVED_68	R	0h	Write 0's for future compatibility. Read returns 0
20:16	ADVWROFFTIME	R/W	6h	ADV# de-assertion time from start cycle time for write accesses [0x00 corresponds to 0 GPMC.FCLK cycle, 0x01 corresponds to 1 GPMC.FCLK cycle, &, 0x1F corresponds to 31 GPMC.FCLK cycles]
15:13	RESERVED_69	R	0h	Write 0's for future compatibility. Read returns 0
12:8	ADVRDOFFTIME	R/W	5h	ADV# de-assertion time from start cycle time for read accesses[0x00 corresponds to 0 GPMC.FCLK cycle, 0x01 corresponds to 1 GPMC.FCLK cycle, &, 0x1F corresponds to 31 GPMC.FCLK cycles]
7	ADVEXTRADELAY	R/W	0h	ADV# Add Extra Half GPMC.FCLK cycle 1 ADV# Timing control signal is delayed of half GPMC.FCLK clock cycle 0 ADV# Timing control signal is not delayed
6:4	ADVAADMUXONTIME	R/W	1h	ADV# assertion for first address phase when using the AAD-Mux protocol
3:0	ADVONTIME	R/W	4h	ADV# assertion time from start cycle time [0x0 corresponds to 0 GPMC.FCLK cycle, 0x1 corresponds to 1 GPMC.FCLK cycle, &, 0xF corresponds to 15 GPMC.FCLK cycles]