SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.9.2.24 GPMC_CONFIG6 Register

9.2.24.1 GPMC_CONFIG6 Register (Offset = 74h) [reset = 8F070000h]

WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration

Offset = Base + (j * 30h); where j = 0 to 3d

Table 5-1214 Instance Table

Instance Name	Physical Address
GPMC0	4840 0074h + formula

Figure 5-602 GPMC_CONFIG6 Name Register

31	30	29	28	27	26	25	24
RESERVED	RESERVED_0		WRACCESSTIME
R/W	R		R/W
1h	0h		Fh
23	22	21	20	19	18	17	16
RESERVED_155				WRDATAONADMUXBUS
R				R/W
0h				7h
15	14	13	12	11	10	9	8
RESERVED_1				CYCLE2CYCLEDELAY
R				R/W
0h				0h
7	6	5	4	3	2	1	0
CYCLE2CYCLESAMECSEN	CYCLE2CYCLEDIFFCSEN	RESERVED_156		BUSTURNAROUND
R/W	R/W	R		R/W
0h	0h	0h		0h

Table 5-1215 GPMC_CONFIG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	1h	TI Internal use - Do not modify
30:29	RESERVED_0	R	0h	Write 0's for future compatibility. Read returns 0
28:24	WRACCESSTIME	R/W	Fh	Delay from StartAccessTime to the GPMC.FCLK rising edge corresponding the the GPMC.CLK rising edge used by the attached memory for the first data capture [0x00 corresponds to 0 GPMC.FCLK cycle, 0x01 corresponds to 1 GPMC.FCLK cycle, &, 0x1F corresponds to 31 GPMC.FCLK cycles]
23:20	RESERVED_155	R	0h	Write 0's for future compatibility. Read returns 0
19:16	WRDATAONADMUXBUS	R/W	7h	Specifies on which GPMC.FCLK rising edge the first data of the synchronous burst write is driven in the add/data mux bus
15:12	RESERVED_1	R	0h	Write 0's for future compatibility. Read returns 0
11:8	CYCLE2CYCLEDELAY	R/W	0h	Chip select high pulse delay between two successive accesses [0x0 corresponds to 0 GPMC.FCLK cycle, 0x1 corresponds to 1 GPMC.FCLK cycle, &, 0xF corresponds to 15 GPMC.FCLK cycles]
7	CYCLE2CYCLESAMECSEN	R/W	0h	Add Cycle2CycleDelay between two successive accesses to the same chip-select [any access type] 1 Add Cycle2CycleDelay 0 No delay between the two accesses
6	CYCLE2CYCLEDIFFCSEN	R/W	0h	Add Cycle2CycleDelay between two successive accesses to a different chip-select [any access type] 1 Add Cycle2CycleDelay 0 No delay between the two accesses
5:4	RESERVED_156	R	0h	Write 0's for future compatibility Reads returns 0
3:0	BUSTURNAROUND	R/W	0h	Bus turn around latency between two successive accesses to the same chip-select [rd to wr] or to a different chip-select [read to read and read to write] [0x0 corresponds to 0 GPMC.FCLK cycle, 0x1 corresponds to 1 GPMC.FCLK cycle, &, 0xF corresponds to 15 GPMC.FCLK cycles]