SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Chip-select address mapping configuration Note: For CS0, the register reset is 0xf40 while for all the other instances CS1-CS7, the reset is 0xf00.
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Offset = Base + (j * 30h); where j = 0 to 3d
| Instance Name | Physical Address |
|---|---|
| GPMC0 | 4840 0078h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_171 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_171 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_171 | MASKADDRESS | ||||||
| R | R/W | ||||||
| 0h | Fh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_172 | CSVALID | BASEADDRESS | |||||
| R | R/W | R/W | |||||
| 0h | 1h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | RESERVED_171 | R | 0h | Write 0's for future compatibility. Read returns 0 |
| 11:8 | MASKADDRESS | R/W | Fh | Chip-select mask address |
| 7 | RESERVED_172 | R | 0h | Write 0's for future compatibility. Read returns 0 |
| 6 | CSVALID | R/W | 1h | Chip-select enable [reset value is 1 for CS0 and 0 for CS1-7] 1 Chip-select enabled 0 Chip-select disabled |
| 5:0 | BASEADDRESS | R/W | 0h | Chip-select base address |