SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.5.2.7 DAC_DACTRIM Register

5.2.7.1 DAC_DACTRIM Register (Offset = Ch) [reset = 0h]

DAC Trim Register.

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Table 3-454 Instance Table

Instance Name	Physical Address
DAC0	5026 000Ch

Figure 3-221 DAC_DACTRIM Name Register

15	14	13	12	11	10	9	8
RESERVED_1				GAIN_TRIM
R				R/W
0h				0h
7	6	5	4	3	2	1	0
OFFSET_TRIM
R/W
0h

Table 3-455 DAC_DACTRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED_1	R	0h	Reserved
11:8	GAIN_TRIM	R/W	0h	DAC Gain Trim. This signed [two's complement] bit field is used to adjust the gain of the DAC. This register will be written with a factory set value during the device boot procedure. 1000 Gain is increased by the equivalent of 0.8% ... 1110 Gain is increased by the equivalent of 0.2% LSB 1111 Gain is increased by the equivalent of 0.1% LSB 0000 Gain is not adjusted 0001 Gain is decreased by the equivalent of 0.1% LSB 0010 Gain is decreased by the equivalent of 0.2% LSB ... 0111 Gain is decreased by the equivalent of 0.7% LSB
7:0	OFFSET_TRIM	R/W	0h	DAC Offset Trim. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications.