SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.12.2.2 SDFM_SDIFLGCLR Register

12.2.2.1 SDFM_SDIFLGCLR Register (Offset = 4h) [reset = 0h]

SD Module Interrupt Flag Clear Bits:

Writing a "1" will clear the respective flag bit in the SDIFLG register.
Writes of "0" are ignored.

Note: If user writes a "1" to clear a bit on the same cycle that the hardware is trying to set the bit to "1", then hardware has priority and the bit will not be cleared.

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Table 3-1131 Instance Table

Instance Name	Physical Address
SDFM0	5026 8004h
SDFM1	5026 9004h

Figure 3-532 SDFM_SDIFLGCLR Name Register

31	30	29	28	27	26	25	24
MIF	RESERVED_1
R/W1TS	R
0h	0h
23	22	21	20	19	18	17	16
SDFFINT4	SDFFINT3	SDFFINT2	SDFFINT1	SDFFOVF4	SDFFOVF3	SDFFOVF2	SDFFOVF1
R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
AF4	AF3	AF2	AF1	MF4	MF3	MF2	MF1
R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
FLT4_FLG_CEVT2	FLT4_FLG_CEVT1	FLT3_FLG_CEVT2	FLT3_FLG_CEVT1	FLT2_FLG_CEVT2	FLT2_FLG_CEVT1	FLT1_FLG_CEVT2	FLT1_FLG_CEVT1
R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS
0h	0h	0h	0h	0h	0h	0h	0h

Table 3-1132 SDFM_SDIFLGCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31	MIF	R/W1TS	0h	Flag-clear bit for SDFM Master Interrupt flag. Writing a 1 to clear MIF flag in SDIFLG register Writes of "0" are ignored. Note: If the MIF flag is cleared and other Interrupts are still pending, MIF will again be set to 1 on the following SysClk cycle, and the INT output will be reasserted [pulsed low]
30:24	RESERVED_1	R	0h	Reserved
23	SDFFINT4	R/W1TS	0h	SDFIFO data ready Interrupt flag-clear bit for Ch4
22	SDFFINT3	R/W1TS	0h	SDFIFO data ready Interrupt flag-clear bit for Ch3
21	SDFFINT2	R/W1TS	0h	SDFIFO data ready Interrupt flag-clear bit for Ch2
20	SDFFINT1	R/W1TS	0h	SDFIFO data ready Interrupt flag-clear bit for Ch1
19	SDFFOVF4	R/W1TS	0h	SDFIFO overflow clear Ch4
18	SDFFOVF3	R/W1TS	0h	SDFIFO overflow clear Ch3
17	SDFFOVF2	R/W1TS	0h	SDFIFO overflow clear Ch2
16	SDFFOVF1	R/W1TS	0h	SDFIFO overflow clear Ch1
15	AF4	R/W1TS	0h	Flag-clear bit for Acknowledge flag for Filter 4
14	AF3	R/W1TS	0h	Flag Clear bit for AF3
13	AF2	R/W1TS	0h	Flag Clear bit for AF2
12	AF1	R/W1TS	0h	Flag Clear bit for AF1
11	MF4	R/W1TS	0h	Flag Clear bit for MF4
10	MF3	R/W1TS	0h	Flag Clear bit for MF3
9	MF2	R/W1TS	0h	Flag Clear bit for MF2
8	MF1	R/W1TS	0h	Flag Clear bit for MF1
7	FLT4_FLG_CEVT2	R/W1TS	0h	Flag Clear bit for FLT4_FLG_CEVT2
6	FLT4_FLG_CEVT1	R/W1TS	0h	Flag Clear bit for FLT4_FLG_CEVT1
5	FLT3_FLG_CEVT2	R/W1TS	0h	Flag Clear bit for FLT3_FLG_CEVT2
4	FLT3_FLG_CEVT1	R/W1TS	0h	Flag Clear bit for FLT3_FLG_CEVT1
3	FLT2_FLG_CEVT2	R/W1TS	0h	Flag Clear bit for FLT2_FLG_CEVT2
2	FLT2_FLG_CEVT1	R/W1TS	0h	Flag Clear bit for FLT2_FLG_CEVT1
1	FLT1_FLG_CEVT2	R/W1TS	0h	Flag Clear bit for FLT1_FLG_CEVT2
0	FLT1_FLG_CEVT1	R/W1TS	0h	Flag Clear bit for FLT1_FLG_CEVT1