SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
SD Control Register.
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| Instance Name | Physical Address |
|---|---|
| SDFM0 | 5026 8008h |
| SDFM1 | 5026 9008h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_3 | RESERVED_2 | MIE | RESERVED_1 | ||||
| R | R | R/W | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_1 | HZ4 | HZ3 | HZ2 | HZ1 | |||
| R | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED_3 | R | 0h | Reserved |
| 14 | RESERVED_2 | R | 0h | Reserved |
| 13 | MIE | R/W | 0h | Master SDy_ERR interrupt enable 0:SDy_ERR Interrupt and interrupt flags are disabled 1:SDy_ERR Interrupt and interrupt flags are enabled |
| 12:4 | RESERVED_1 | R | 0h | Reserved |
| 3 | HZ4 | R/W1TS | 0h | Flag Clear bit for HZ4 |
| 2 | HZ3 | R/W1TS | 0h | Flag Clear bit for HZ3 |
| 1 | HZ2 | R/W1TS | 0h | Flag Clear bit for HZ2 |
| 0 | HZ1 | R/W1TS | 0h | Flag Clear bit for HZ1 |