SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Data Filter Parameter Register for Ch3.
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| Instance Name | Physical Address |
|---|---|
| SDFM0 | 5026 8062h |
| SDFM1 | 5026 9062h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_1 | SDSYNCEN | SST | AE | FEN | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DOSR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:13 | RESERVED_1 | R | 0h | Reserved |
| 12 | SDSYNCEN | R/W | 0h | PWM synchronization [SDSYNC] of data filter 0:PWM synchronization of data filter is disabled 1:PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs |
| 11:10 | SST | R/W | 0h | Data filter structure 00:Data filter runs with a Sincfast structure 01:Data filter runs with a Sinc1 structure 10:Data filter runs with a Sinc2 structure 11:Data filter runs with a Sinc3 structure |
| 9 | AE | R/W | 0h | Data filter Acknowledge Enable 0:Acknowledge flag is disabled for the particular filter 1:Acknowledge flag is enabled for the particular filter |
| 8 | FEN | R/W | 0h | Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled, DOSR counter held in reset, filter data erased. Also resets FIFO pointers and clears the FIFO |
| 7:0 | DOSR | R/W | 0h | Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256. |