SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
SD Filter Sync control for Ch3.
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| Instance Name | Physical Address |
|---|---|
| SDFM0 | 5026 807Ch |
| SDFM1 | 5026 907Ch |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_1 | WTSCLREN | FFSYNCCLREN | WTSYNCLR | ||||
| R | R/W | R/W | R/W | ||||
| 0h | 1h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WTSYNFLG | WTSYNCEN | SYNCSEL | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:11 | RESERVED_1 | R | 0h | Reserved |
| 10 | WTSCLREN | R/W | 1h | WTSYNFLG Clear-on-FIFOINT Enable 0:WTSYNFLG can only be cleared manually [using WTSYNCLR bit] 1:WTSYNFLG is cleared automatically on SDFFINT |
| 9 | FFSYNCCLREN | R/W | 0h | FIFO Clear-on-SDSYNC Enable 0:SDFIFO is not automaticaly cleared upon receiving SDSYNC 1:SDFIFO is automaticaly cleared upon receiving SDSYNC |
| 8 | WTSYNCLR | R/W | 0h | Wait-for-Sync Flag Clear [always reads 0] 0:Write of 0 has no effect 1:Write of 1 clears WTSYNFLG |
| 7 | WTSYNFLG | R | 0h | Wait-for-Sync Flag 0:SDSYNC event has not occurred 1:SDSYNC event occurred. |
| 6 | WTSYNCEN | R/W | 0h | Wait-for-Sync Enable 0:Incoming Data written to SDFIFO on every Data-Ready [DR] Event 1:Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs |
| 5:0 | SYNCSEL | R/W | 0h | Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table |