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JAJSKX2A August 2019 – May 2021 TPS53676

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8.2.3 Detailed Design Procedure

The following steps illustrate the key components selection for the 0.88-V / 250-A, 1-V / 30-A ASIC application.

Inductor Selection

Smaller inductance yields better transient performance, but leads to higher ripple current and lower efficiency. Higher inductance has the opposite effect. It is common practice to limit the ripple current to between 20%-40% of maximum per-phase current for balanced performance. In this design example, 30% of the maximum per-phase current is used for channel A.

Equation 48.

{ΔI}_{RIPPLE(target)} = \frac{I_{CC(MAX)}}{N_{Φ}} \times 30 % = \frac{250 A}{6 phases} \times 0.3 = 12.5 A

Equation 49.

L_{target} = \frac{V_{OUT} \times(V_{in(max)} - V_{OUT})}{V_{in(max)} \times {ΔI}_{RIPPLE(target)} \times f_{SW}} = \frac{0.88 V \times(13.2 V - 0.88 V)}{13.2 V \times 12.5 A \times 500 kHz} = 0.131 μH

Considering the variation and derating of the inductance and a standard inductor value of 150nH with DCR 0.125 mΩ, is selected. Then use Equation 50 to re-calculate the actual output ripple.

Equation 50.

I_{RIPPLE(actual)} = \frac{V_{OUT} \times (V_{in(max)} - V_{OUT})}{V_{in(max)} \times f_{SW} \times L_{actual}} = \frac{0.88 V \times(13.2 V - 0.88 V)}{13.2 V \times 500 kHz \times 0.150 μH} = 10.9 A

With same design procedure for channel B, a standard inductor value of 150 nH with DCR 0.125 mΩ from ITG is chosen.

Output Capacitor Selection

Generally, consider output ripple and output voltage deviation during load transient when selecting output capacitors.

When available, follow the output capacitance recommendation for the load ASIC reference design. With TPS53676 device, it is possible to meet the load transient with lower output capacitance due to the high-speed nature of DCAP+ control. Output Capacitor Recommendations is the output capacitance recommendation for the above rail specification.

Table 8-2 Output Capacitors

Capacitor location	Channel A	Channel B
Bulk capacitors near power stages	12x 470 μF / 2.5V / 3mΩ ESR	2x 470 μF / 2.5V / 3mΩ ESR
Top side	24x 220 μF / 4V / X5R/ 1206 18x 100 μF / 4V / X5R / 1206	4x 220 μF / 4V / X5R / 1206 3x 100 μF / 4V / X5R / 1206
Bottom side	24x 220 μF / 4V / X5R / 1206 18x 100 μF / 4V / X5R / 1206	4x 220 μF / 4V / X5R / 1206 3x 100 μF / 4V / X5R / 1206
Total output capacitance	19.8 mF	1874 μF

Select Per-Phase Valley Current Limit

The equation below shows the calculation of per-phase valley current limit based on maximum processor current, the operating phase number and per-phase current ripple ΔI_{RIPPLE(actual)}.

For the channel A,

Equation 51.

I_{OCL} = K_{margin} \times \frac{I_{CC(max)}}{N_{Φ}} - \frac{{ΔI}_{RIPPLE}}{2} = 1.25 \times \frac{250 A}{6 phases} - \frac{10.9 A}{2} = 46.6 A

Where K_margin is the maximum operating margin factor. Choose 125% margin to avoid triggering current limit during load transient events. For this design, choose the 47A valley current limit for channel A.

Equation 52.

I_{SAT(min)} = I_{OCL} + Δ I_{RIPPLE} = 47 A + 10.9 A = 57.9 A

The calculation above shows the minimum saturation current for inductor. Using same design procedure, the valley current limit for channel B is selected to be 26 A.

Set USR threshold to improve load transient performance

There are two levels of undershoot reduction (USR1, USR2) options. USR1 enables up to 3, 4, 5 or all normal phases and USR2 enables all available phases. To select the proper value, start with each USR threshold set to be disabled, and then systematically lower the threshold, enabling fast-phase-addition to meet the load transient requirement.

For this design, phase shedding is disabled. USR1 and USR2 are selected to be disabled for both channel A and channel B.

Input Current Sensing (Shunt/ Calculated Iin/ Inductor DCR)

TPS53676 has three input current sensing options: shunt current sensing, calculated input current sensing and inductor DCR current sensing. Either option may be chosen for precision input current reporting.

Shunt current sensing

In this design, the external shunt resistor 0.5 mΩ ± 1%, 3 W, 4026 package is selected. Once properly calibrated, Input current reporting is within the tolerance target.

Calculated input current sensing

TPS53676 includes an option to impute input current for situations in which the addition of a shunt or input inductor is prohibitive. Connect pins 46 (VIN_CSNIN) and 47 (CSPIN) together, and place a minimum 1 μF effective capacitance bypass cap from pin 46 to GND, then connect pin 46 to input supply (12 V nominally) before input inductor. Configure the calculated input current option through the NVM settings in MFR_SPECIFIC_ED (MISC OPTIONS).

Inductor DCR Current Sensing

This section describes the procedure to determine an inductor DCR thermal compensation network design. The image below shows a typical DCR sensing circuit. From the equations below, when the time constant of the RC network is equal to the L/R time constant of the inductor, the capacitor voltage V_C across the C_SENSE capacitor can be used to obtain the inductor current. However, inductor windings have a positive temperature coefficient of approximately 3900 ppm/°C. So an NTC thermistor is used to cancel thermal variation from the inductor DCR.

The design goal is for the DCR value to be invariant with the temperature. Therefore, the voltage across sense capacitor would be only dependent on the inductor current over the temperature range of interest.

Figure 8-5 Input DCR Network

Equation 53.

C_{SENSE} \times R_{EQ} = \frac{L}{R_{DCR}}

Equation 54.

I_{IN} \times R_{DCR} = V_{DCR}

The equivalent resistance of the R_SEQU, R_NTC, R_SERIES and R_PAR values is given by R_EQ. Use the equations below to derive the values of R_SEQU, R_NTC, R_SERIES and R_PAR.

Equation 55.

R_{EQ} = \frac{R_{P_N}}{R_{P_N} + R_{SEQU}}

Equation 56.

R_{P_N} = \frac{R_{PAR} \times(R_{NTC} + R_{SERIES})}{R_{PAR} + R_{NTC} + R_{SERIES}}

Equation 57.

V_{C} = V_{DCR} \times R_{EQ} = \frac{I_{IN} \times R_{DCR} \times R_{P_N}}{R_{P_N} + R_{SEQU}} = β \times I_{IN}

Finally the value of β, given in the equation below, represents the effective current sense gain after thermal compensation. This value can be used as the sense element resistance to derive the PMBus settings as described in Input current calibration (measured).

Equation 58.

β = \frac{R_{DCR} \times R_{P_N}}{R_{P_N} + R_{SEQU}}

For this design, select thermistor RNTC as 1 kΩ, 5%, 0603, B-constant is 3650k, P/N: NCP18XQ102J03B from Murata. Select C_SENSE as 1 μF X7R or better dielectric (C0G preferred).

In order to solve the value of R_SEQU, R_SERIES and R_PAR, the β at three temperature points are set equal. set β = 0.15 mΩ equally at temperature 0 °C, 25 °C and 75 °C. With the calculation, three resistors value can be found as R_SEQU = 332 Ω, R_SERIES = 432 Ω, R_PAR = 1.40 kΩ.

Figure 8-6 Inductor DCR sensing voltage over temperature

TI offers an application note and excel spreadsheet to streamline input DCR netowrk calculations. Contact your local field/sales representative to get a copy of the document.

Loop compensation design

5 mΩ: Typical gain from power stage current sense
ACLL: Programmable AC load line, provides direct output voltage feedback.
DCLL: Programmable DC load line, provides adaptive voltage positioning
K_DIV : Fixed scalar with value of 0.5
τ_INT : Programmable integration time constant, adjustable from 1µs to 16 µs (scale = 1 µs)
K_INT : Programmable integration gain which can be adjustable from 0.5x, 1x, 1.5x, 2x
K_AC : Programmable AC gain which is adjustable from 0.5x, 1x, 1.5x, 2x
V_RAMP : Programmable ramp voltage which is adjustable from 80 mV to 320 mV(scale = 40 mV)

For this design, the optimal loop compensation values were derived by tuning. The final valuea are listed .

Table 8-3

PARAMETER	Channel A	Channel B
DCLL	0.0 mΩ	0.0 mΩ
ACLL	0.2 mΩ	0.5 mΩ
τ_INT	1 µs	7 µs
K_INT	2.0	1.0
K_AC	1.0	1.0
V_RAMP	320 mV	200 mV

Select ADDR pin resistors

Based on the design requirements of PMBus address select the upper and lower ADDR pin resistors, R_HA and R_LA according to ADDR pin decoding.

Table 8-4

PMBus address	R_HA	R_LA
96d / C0h	110 kΩ	37.4 kΩ

Select the boot voltage V_BOOT for each channel

The boot voltage for channel A is determined by pinstrapping on the BOOT_CHA pin. Based on BOOT_CHA pinstrap decoding, select R_HB = 20.0 kΩ and R_LB = 59.0 kΩ to select 0.88 V as the channel A boot voltage.

The boot voltage for channel B is stored in NVM. Update the NVM value for VOUT_COMMAND to 1.0 V , and store the value to non-volatile memory.