JAJSKX2A August 2019 – May 2021 TPS53676
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PMBus Timing and Physical Characteristics | ||||||
tPMB-BUF | PMBus Free time between STOP and START conditions (1) | 0.5 | µs | |||
tPMB-HD-STA | Hold time after Repeated Start Condition (1) | 0.26 | µs | |||
tPMB-SU-STO | Stop condition Setup time (1) | 0.26 | µs | |||
tPMB-HD-DAT | SMB_DIO Hold Time (1) (2) | 0 | µs | |||
tPMB-SU-DAT | SMB_DIO Setup Time | 50 | ns | |||
tPMB-TIMEOUT | SMB_CLK low timeout (1) (3) | 25 | 35 | ms | ||
tPMB-LOW | SMB_CLK low time (1) | 0.5 | µs | |||
tPMB-HIGH | SMB_CLK high time (1) (4) | 0.26 | 50 | µs | ||
tPMB-LOW-SEXT | Maximum clock stretching time (slave) (1) (5) | 25 | ms | |||
tPMB-LOW-MEXT | Maximum clock stretching time (master) (1) (6) | 10 | ms | |||
tR-PMB | SMB_DIO/SMB_CLK rise time, ( VIL(MAX)-150 mV to VIH(MIN)+150 mV) (1) | 100 kHz Class | 1000 | ns | ||
400 kHz Class | 300 | ns | ||||
1000 kHz Class | 120 | ns | ||||
tF-PMB | SMB_DIO/SMB_CLK fall time, ( VIH(MIN)+150 mV to VIL(MAX) + 150 mV) (1) | 100 kHz Class | 1000 | ns | ||
400 kHz Class | 300 | ns | ||||
1000 kHz Class | 120 | ns | ||||
tPMB-REJ | Noise spike suppression-time (1) (7) | 50 | ns | |||
ILK-PMB-BUS | Input leakage per PMBus segment (1) | -200 | 200 | µA | ||
ILK-PMB-PIN | Input leakage for PMBus pins | -10 | 10 | µA | ||
CPMB-BUS | PMBus Bus Capacitance (1) | 400 | pF | |||
CPMB-PIN | PMBus Pin Capacitance (1) | 10 | pF | |||
VPULLUP_PMBus | PMBus interface pull ups (1) | 1.62 | 3.63 | V | ||
VIL_PMBus | SMB_DIO, SMB_CLK Input logic low | 0.8 | V | |||
VIH_PMBus | SMB_DIO, SMB_CLK Input logic high | 1.35 | V | |||
VHYST_PMBus | Hysteresis voltage | 80 | mV | |||
VOL_PMBus | Low-level output voltage | IOL = -20 mA | 0.4 | V | ||
PMBCLKR | PMBus clock frequency range (1) | PMBus Clock Requirements (9) | 0.05 | 2 | MHz | |
AVSBus Timing and Physical Characteristics | ||||||
tP-AVS | AVS_CLK Active Clock Period (1) | 20 | 200 | ns | ||
tHIGH-AVSCLK | AVS_CLK high period (1) | 10 | ns | |||
tLOW-AVSCLK | AVS_CLK low period (1) | tP-AVS/2 | ns | |||
tTO-AVSCLK | AVS Clock Timeout Delay (1) | Clock idle period before clock timeout condition is recognized | 5 | µs | ||
NPRECLK-AVS | Number of preamble AVSCLK required to accept AVS frame after AVS clock timeout (1) | 2 | cycles | |||
tR-AVSDAT | AVS_MDATA, AVS_SDATA rise time (1) | 3 | ns | |||
tF-AVSDAT | AVS_MDATA, AVS_SDATA fall time (1) | 3 | ns | |||
tPD-AVS | Time for signals to propagate from one device to another (1) | 4 | ns | |||
tCAPT-AVSS | Time from falling clock edge in Master to data capture inside slave (1) | tPD-AVS | 2+tPD-AVS | ns | ||
tSU-AVSS | Time from data-out edge in Master to clock edge in Slave (1) | 2+tPD-AVS | ns | |||
tLAUNCH-AVSS | Time from rising clock edge in Master to data-out transition at Slave's data-out port (1) (8) | 2+tPD-AVS | 8 + tPD-AVS | 14 + tPD-AVS | ns | |
tH-AVSM | Time from capture clock edge in Master to data-out edge in Slave (for next bit) (1) | 2 | tLOW-AVSCLK | ns | ||
ILK-AVS | AVSBus pin (AVS_MDATA, AVS_SDATA, AVS_CLK, AVS_VDDIO) leakage | -10 | 10 | µA | ||
VDDIO-AVSBus | AVS_VDDIO input range | 1.14 | 3.6 | V | ||
VIL-AVSMDA | AVS_MDATA input logic low | 0.4*VDDIO | V | |||
VIH-AVSMDA | AVS_MDATA input logic high | 0.6*VDDIO | V | |||
VOL-AVSSDA | AVS_SDATA output logic low | 0.2*VDDIO | V | |||
VOH-AVSSDA | AVS_SDATA output logic high | 0.8*VDDIO | V | |||
AVSCLKR | AVSBus clock frequency range (1) | AVSBus Clock Requirements | 5 | 50 (10) | MHz |