CDCLVD2108

Name: CDCLVD2108
Brand: TI
SKU: CDCLVD2108
Price: 6.376 USD

AKTIV

Jitterarmer Dual-1:8-Universal-zu-LVDS-Puffer

Jetzt bestellen

Datenblatt

document-pdfAcrobat Dual 1:8 Low Additive Jitter LVDS Buffer datasheet (Rev. C) (Englisch)

CDCLVD2108

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of outputs

16

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

50

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

16

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

50

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

VQFN (RGZ)

48

49 mm² 7 x 7

Dual 1:8 Differential Buffer
Low Additive Jitter <300 fs RMS in
10 kHz to 20 MHz
Low Within Bank Output Skew of 50 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Eight Outputs
Total of 16 LVDS Outputs, ANSI EIA/TIA-644A
Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625V Device Power Supply
LVDS Reference Voltage, V_{AC_REF},
Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

Dual 1:8 Differential Buffer
Low Additive Jitter <300 fs RMS in
10 kHz to 20 MHz
Low Within Bank Output Skew of 50 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Eight Outputs
Total of 16 LVDS Outputs, ANSI EIA/TIA-644A
Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625V Device Power Supply
LVDS Reference Voltage, V_{AC_REF},
Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15). Each buffer block consists of one input and 8 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2108 is specifically designed for driving 50- transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN) outputs can be either disabled or enabled. If the EN pin is left open all outputs are active, if switched to a logical "0" all outputs are disabled (static logical 0), if switched to a logical "1", OUT (8..15) are switched off and OUT (0..7) are active. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2108 is packaged in small 48-pin, 7-mm × 7-mm QFN package.

The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15). Each buffer block consists of one input and 8 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2108 is specifically designed for driving 50- transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (V_{AC_REF}) should be applied to the unused negative input pin.

Using the control pin (EN) outputs can be either disabled or enabled. If the EN pin is left open all outputs are active, if switched to a logical "0" all outputs are disabled (static logical 0), if switched to a logical "1", OUT (8..15) are switched off and OUT (0..7) are active. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2108 is packaged in small 48-pin, 7-mm × 7-mm QFN package.

filter

Andere Taktpuffer suchen

Herunterladen Video mit Transkript ansehen Video

Alle anzeigen 1

Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Data sheet	Dual 1:8 Low Additive Jitter LVDS Buffer datasheet (Rev. C)		21 Dez 2010

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

CDCLVD2106EVM — CDCLVD2106-Evaluierungsmodul

The CDCLVD1212/CDCLVD2106 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1212 only). The devices also feature on-chip bias generators that can (...)

Benutzerhandbuch: PDF

Nicht verfügbar auf TI.com

Simulationsmodell

CDCLVD2108 IBIS Model (Rev. B)

SLLM096B.ZIP (15 KB) - IBIS Model

Herunterladen

Designtool

CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect

Der Taktbaum-Architekt ist ein Taktbaum-Synthesetool, das Ihren Designprozess optimiert, indem es Taktbaumlösungen auf der Grundlage Ihrer Systemanforderungen erzeugt. Das Tool zieht Daten aus einer umfangreichen Datenbank von Taktgeberprodukten, um eine Multi-Chip-Taktlösung auf Systemebene zu (...)

Jetzt entwickeln

Designtool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Unterstützte Produkte und Hardware

Download-Optionen

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)

Anfordern

Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
VQFN (RGZ)	48	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

CDCLVD2108

Jitterarmer Dual-1:8-Universal-zu-LVDS-Puffer

CDCLVD2108

Produktdetails

Ähnliche Produkte, die für Sie interessant sein könnten

Selbe Funktionalität wie der verglichene Baustein bei gleicher Anschlussbelegung

Ähnliche Funktionalität wie verglichener Baustein

Technische Dokumentation

Design und Entwicklung

CDCLVD2106EVM — CDCLVD2106-Evaluierungsmodul

CDCLVD2108 IBIS Model (Rev. B)

CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Unterstützte Produkte und Hardware

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

Bestellen & Qualität

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Videoreihe

Videos

Download-Möglichkeiten

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Taktpuffer

Taktgeneratoren

Takt-Jitter-Cleaner

Oszillatoren

HF-PLLs und Synthesizer

Hardware-Entwicklung

Dokumentation

Versionsinformationen

Neuheiten