XMICR-3P-LMX2492
Overview
X-MWblocks consist of RF and Microwave “Drop-In” components that can be used individually for prototyping or in production assemblies. X-MWblocks are easy to test, integrate, align, and configure to 60 GHz and beyond. No messy Sweat Soldering or Silver Epoxy processes are required. X-MWblocks are highly characterized with S-Parameter models and connect with a patented solder-less interconnect technology.
This X-MWblock incorporates the LMX2492 phased lock loop. The LMX2492 is a 500MHz to 14GHz wideband, low noise fractional-N PLL with ramp/chirp generation capability.
RF PLLs & synthesizers
Order & start development
XM-C6K5-0409D — Phase lock loops
XM-C6K5-0409D — Phase lock loops
PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool
Supported products & hardware
Products
Clock buffers
Clock generators
Clock jitter cleaners
Oscillators
RF PLLs & synthesizers
Hardware development
Evaluation board
PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool
Products
Clock buffers
Clock generators
Clock jitter cleaners
Oscillators
RF PLLs & synthesizers
Hardware development
Evaluation board
Documentation
Release Information
Added cascaded phase noise analysis
What's new
- Added cascaded phase noise analysis
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
Supported products & hardware
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
Oscillators
RF PLLs & synthesizers
Hardware development
Evaluation board
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.6 installer binary for Windows operating system
Products
Clock buffers
Clock generators
Clock jitter cleaners
Clock network synchronizers
Oscillators
RF PLLs & synthesizers
Hardware development
Evaluation board
Documentation
TICS Pro 1.7.7.6 Software Manifest
TICS Pro 1.7.7.6 Release Notes
Release Information
Added Features
LMK5Bxxyyy, LMK5Cxxyyy
- Warnings and errors improved, particularly corrective suggestions
- REFx_FREQ=0 automatically disables DPLL reference input selection for that input
- Input validation enabled and disabled by start page settings, including 1PPS
- APLL reference selection moved to Step 5, just before clock output definition
- Quick-set multiple outputs to the same settings on frequency planner
- BAW VCO allows some ppm deviation
- Force SYSREF option on OUT0/1
- Expose DPLLx_LCK_TIMER field
- Match LMK05318B EEPROM page design
- .EPR export option
- EEPROM SRAM programming generation support
- For complete changelist, see release notes
LMK3H0102
- Configuration search tool
- Wizard: voltage selection option
Bug Fixes
- LMK04832-SP, LMK04832-SEP, LMK04714-Q1, LMK04368-EP - PD_FIN0 corrected to FIN0_PD
- LMK3H0102 - Several wizard bugfixes
Known Issues
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
Related design resources
Hardware development
EVALUATION BOARD
Software development
APPLICATION SOFTWARE & FRAMEWORK
Support & training
Video series
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