PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
LMK1D2106: 6-mm × 6-mm, 40-pin VQFN (RHA)
LMK1D2108: 7-mm × 7-mm, 48-pin VQFN (RGZ)
The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one input and a maximum of 6 (LMK1D2106) or 8 (LMK1D2108) LVDS outputs. The inputs can either be LVDS, LVPECL, HCSL, CML, or LVCMOS.
The LMK1D210x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).
Using the control pin (EN), output banks can either be enable or disabled. If this pin is left open, both bank outputs are enabled. If the control pin is switched to a logic "0", both bank outputs are disabled (static logic "0"). If the control pin is switched to a logic "1", the outputs of one bank are disabled while the outputs of the other bank are enabled. The part also supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | LMK1D210x Low Additive Jitter LVDS Buffer datasheet (Rev. A) | PDF | HTML | 28 ene 2022 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.