LMK04826BEVM
LMK04826BEVM 評估模組
LMK04826BEVM
概覽
The LMK04826BEVM and LMK04828BEVM supports the LMK04820 family of products, the industry's highest performance clock conditioners with JEDEC JESD204B support. The dual loop PLLatinum™ architecture enables sub-100 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO).
The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock and SYSREF generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO.
The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
特點
- JEDEC JESD204B Support
- Ultra-low RMS Jitter Performance
- Dual loop Architecture
- 3 redundant input clocks with LOS
- Precision digital delay, fixed or dynamically adjustable
- Evaluation kit includes USB2ANY module for USB connection to the evaluation board.
時鐘抖動清除器
開始使用
- Order the CDCE6214-Q1EVM
- Download and install TICSPRO-SW
- Read the CDCE6214-Q1EVM user’s guide
- Configure registers on TICSRPRO-SW
訂購並開始開發
LMK04826BEVM — LMK04826BEVM Evaluation Module
LMK04826BEVM — LMK04826BEVM Evaluation Module
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
支援產品和硬體
產品
RF PLL 與合成器
振盪器
時脈網路同步器
時鐘抖動清除器
時鐘產生器
時鐘緩衝器
硬體開發
開發板
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.6 installer binary for Windows operating system
產品
RF PLL 與合成器
振盪器
時脈網路同步器
時鐘抖動清除器
時鐘產生器
時鐘緩衝器
硬體開發
開發板
文件
TICS Pro 1.7.7.6 Software Manifest
TICS Pro 1.7.7.6 Release Notes
版本資訊
Added Features
LMK5Bxxyyy, LMK5Cxxyyy
- Warnings and errors improved, particularly corrective suggestions
- REFx_FREQ=0 automatically disables DPLL reference input selection for that input
- Input validation enabled and disabled by start page settings, including 1PPS
- APLL reference selection moved to Step 5, just before clock output definition
- Quick-set multiple outputs to the same settings on frequency planner
- BAW VCO allows some ppm deviation
- Force SYSREF option on OUT0/1
- Expose DPLLx_LCK_TIMER field
- Match LMK05318B EEPROM page design
- .EPR export option
- EEPROM SRAM programming generation support
- For complete changelist, see release notes
LMK3H0102
- Configuration search tool
- Wizard: voltage selection option
Bug Fixes
- LMK04832-SP, LMK04832-SEP, LMK04714-Q1, LMK04368-EP - PD_FIN0 corrected to FIN0_PD
- LMK3H0102 - Several wizard bugfixes
Known Issues
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| 證書 | LMK04826BEVM EU Declaration of Conformity (DoC) | 2019/1/2 | ||||
| 使用指南 | LMK04826/28 User’s Guide (Rev. B) | 2018/3/13 |