產品詳細資料

Number of outputs 8 Output type CML, HCSL, LVCMOS, LVDS, LVPECL Output frequency (max) (MHz) 1000 Core supply voltage (V) 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type CML, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Features I2C, Integrated EEPROM, Pin programmable Rating Catalog
Number of outputs 8 Output type CML, HCSL, LVCMOS, LVDS, LVPECL Output frequency (max) (MHz) 1000 Core supply voltage (V) 3.3 Output supply voltage (V) 1.8, 2.5, 3.3 Input type CML, LVDS, LVPECL, XTAL Operating temperature range (°C) -40 to 85 Features I2C, Integrated EEPROM, Pin programmable Rating Catalog
WQFN (RHS) 48 49 mm² 7 x 7
  • Ultra-low noise, high performance
    • Jitter: 100fs RMS typical, FOUT > 100MHz
    • PSNR: –80dBc, robust supply noise immunity
  • Flexible device options
    • Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS outputs, or any combination
    • Pin mode, I2C mode, and EEPROM mode
    • 71-pin selectable pre-programmed default start-up options
  • Dual inputs with automatic or manual selection
    • Crystal input: 10MHz to 52MHz
    • External input: 1MHz to 300MHz
  • Frequency margining options
    • Fine frequency margining (±50ppm typical) using low-cost pullable crystal reference
    • Glitchless coarse frequency margining (%) using output dividers
  • Other features
    • Supply: 3.3V core, 1.8V, 2.5V, 3.3V output
    • Industrial temperature range (–40°C to 85°C)
    • Package: 7mm × 7mm 48-WQFN
  • Ultra-low noise, high performance
    • Jitter: 100fs RMS typical, FOUT > 100MHz
    • PSNR: –80dBc, robust supply noise immunity
  • Flexible device options
    • Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS outputs, or any combination
    • Pin mode, I2C mode, and EEPROM mode
    • 71-pin selectable pre-programmed default start-up options
  • Dual inputs with automatic or manual selection
    • Crystal input: 10MHz to 52MHz
    • External input: 1MHz to 300MHz
  • Frequency margining options
    • Fine frequency margining (±50ppm typical) using low-cost pullable crystal reference
    • Glitchless coarse frequency margining (%) using output dividers
  • Other features
    • Supply: 3.3V core, 1.8V, 2.5V, 3.3V output
    • Industrial temperature range (–40°C to 85°C)
    • Package: 7mm × 7mm 48-WQFN

The LMK03328 device is an ultra-low-noise clock generator that has two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fan-out, and pin-selectable configuration states stored in an on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, which can reduce the BOM cost and board area, and can improve reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.

The LMK03328 device is an ultra-low-noise clock generator that has two fractional-N frequency synthesizers with integrated VCOs, flexible clock distribution and fan-out, and pin-selectable configuration states stored in an on-chip EEPROM. The device can generate multiple clocks for various multi-gigabit serial interfaces and digital devices, which can reduce the BOM cost and board area, and can improve reliability by replacing multiple oscillators and clock distribution devices. The ultra-low-jitter reduces bit error rate (BER) in high-speed serial links.

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重要文件 類型 標題 格式選項 日期
* Data sheet LMK03328 Ultra-Low Jitter Clock Generator With Two Independent PLLs, Eight Outputs, Integrated EEPROM datasheet (Rev. E) PDF | HTML 2024年 9月 17日
Application note Clocking for PCIe Applications PDF | HTML 2023年 11月 28日
Technical article Clock tree fundamentals: finding the right clocking devices for your design PDF | HTML 2021年 3月 24日
Application note Clocking for Medical Ultrasound Systems (Rev. A) PDF | HTML 2020年 9月 30日
Technical article Can a clock generator act as a jitter cleaner? PDF | HTML 2017年 3月 23日
Technical article The five benefits of multifaceted clocking devices PDF | HTML 2016年 5月 17日
Technical article Complete clock-tree solutions that make a hardware designer’s life easier PDF | HTML 2016年 3月 10日
Application note Clocking High Speed Serial Links with LMK033X8 (Rev. A) 2016年 1月 7日
Application note Frequency Margining Using TI High-Performance Clock Generators (Rev. A) 2015年 12月 12日
Technical article How to select an optimal clocking solution for your FPGA-based design PDF | HTML 2015年 12月 9日

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開發板

LMK03328EVM — 具有 2 個 PLL、8 個差動輸出和 2 個輸入的 LMK03328EVM 超低抖動時鐘產生器 EVM

The LMK03328EVM evaluation module provides a complete clocking platform to evaluate the 100-fs RMS jitter performance and pin-/software-configuration modes and features of the Texas Instruments LMK03328 Ultra-Low-Jitter Clock Generator with Dual PLLs, 8 outputs, 2 inputs, and integrated EEPROM.

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使用指南: PDF
TI.com 無法提供
軟體程式設計工具

SNAC069 LMK03328EVM Default EEPROM Image File

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TICSPRO-SW TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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模擬型號

LMK03328 IBIS Model (Rev. B)

SNAM177B.ZIP (88 KB) - IBIS Model
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時鐘樹架構是一款時鐘樹合成工具,可根據您的系統需求產生時鐘樹解決方案,進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料,產生系統級多晶片計時解決方案。
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PLLATINUMSIM-SW PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一,涵蓋我們的類比和電源產品組合,以及特定類比行為模型,且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前,建立完整的終端設備設計和解決方案原型,進而縮短上市時間並降低開發成本。 

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WQFN (RHS) 48 Ultra Librarian

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