LMK04616
- Dual-loop PLL architecture
- Ultra low noise (10 kHz
to 20 MHz):
- 48-fs RMS jitter at 1966.08 MHz
- 50-fs RMS jitter at 983.04 MHz
- 61-fs RMS jitter at 122.88 MHz
- –165-dBc/Hz noise floor at 122.88 MHz
- JESD204B support
- Single shot, pulsed, and continuous SYSREF
-
16 differential output clocks in 8 frequency groups
- Programmable output swing between 700 mVpp to 1600 mVpp
- Each output pair can be configured to SYSREF clock output
- 16-bit channel divider
- Minimum SYSREF frequency of 25 kHz
- Maximum output frequency of 2 GHz
- Precision digital delay, dynamically adjustable
- Digital delay (DDLY) of ½ × clock distribution path frequency (2 GHz maximum)
- 60-ps step analog delay
- 50% duty cycle output divides, 1 to 65535
(even and odd)
- Four reference inputs
- Holdover mode, when inputs are lost
- Automatic and manual switch-over modes
- Loss-of-signal (LOS) detection
- 1.05-W typical power consumption with 16 outputs active
- Operates typically from a 1.8-V (outputs, inputs) and 3.3-V supply (digital, PLL1, PLL2_OSC, PLL2 core)
- Fully integrated programmable loop filter
- PLL2
- PLL2 phase detector rate up to 250 MHz
- OSCin frequency-doubler
- Integrated low-noise VCO
- Internal power conditioning: better than –80 dBc PSRR on VDDO for 122.88-MHz differential outputs
- 3- or 4-wire SPI interface (4-wire is default)
- –40ºC to +85ºC industrial ambient temperature
- Supports 105ºC PCB temperature (measured at thermal pad)
- LMK04616: 10-mm × 10-mm NFBGA-144 package with 0.8-mm pitch
The LMK0461x device family is the industry’s highest performance and lowest power jitter cleaner with JESD204B support. The 16 clock outputs can be configured to drive eight JESD204B converters or other logic devices using device and SYSREF clocks. The 17th output can be configured to provide a signal from PLL2 or a copy from the external VCXO.
Features like fully integrated PLL1 and PLL2 loop filters, a high number of integrated LDOs, digital and analog delay, the flexibility to supply outputs with 3.3V, 2.5V and 1.8V as well as the option to generate multiple SYSREF domains simultaneously makes the device easy to use.
Not limited to JESD204B applications each of the 17 outputs can be configured for traditional clocking systems.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK04616 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs datasheet (Rev. B) | PDF | HTML | 2018/1/9 | ||
| 應用說明 | JESD204B Multi-Device Synchronization Using LMK0461x | PDF | HTML | 2017/8/16 | |||
| 應用說明 | LMK0461x Phase Noise Performance With DC-DC Converters (Rev. B) | 2017/7/20 | ||||
| 應用說明 | SDPLL for LMK046xx Family | 2017/5/15 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
LMK04616EVM — LMK04616 評估模組
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| NFBGA (ZCR) | 144 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。