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LMK05318B

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產品規格表

LMK05318B

現行
產品規格表 立即訂購

產品詳細資料

Function Clock network synchronizer Number of outputs 8 Output type CML, HCSL, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features I2C, Integrated EEPROM, Pin programmable, SPI Output frequency (min) (MHz) 0.000001 Output frequency (max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 85 Number of input channels 2
Function Clock network synchronizer Number of outputs 8 Output type CML, HCSL, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features I2C, Integrated EEPROM, Pin programmable, SPI Output frequency (min) (MHz) 0.000001 Output frequency (max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 85 Number of input channels 2
VQFN (RGZ) 48 49 mm² 7 x 7
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 32fs typical RMS jitter at 312.5MHz with 4MHz 1st order high-pass filter (HPF)
    • 44fs typical RMS jitter at 156.25MHz with 4MHz 1st order HPF
    • 50fs typical/ 80fs maximum RMS jitter at 312.5MHz
    • 60fs typical/ 90fs maximum RMS jitter at 156.25MHz
  • One high-performance Digital Phase-Locked Loop (DPLL) paired with two Analog Phase-Locked Loops (APLLs):
    • 1mHz to 4kHz programmable DPLL loop bandwidth
    • < 1ppt per step DCO adjustment for IEEE 1588 PTP clock steering
  • Two differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • Eight differential outputs with programmable AC-LVPECL, AC-CML, AC-LVDS, HSCL, and 1.8V LVCMOS output formats.
    • 1Hz (1PPS) to 1250MHz output frequency
    • PCIe Gen 1 to 6 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • 3.3V core supply and 1.8V, 2.5V, or 3.3V output supply
  • –40°C to +85°C operating temperature
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 32fs typical RMS jitter at 312.5MHz with 4MHz 1st order high-pass filter (HPF)
    • 44fs typical RMS jitter at 156.25MHz with 4MHz 1st order HPF
    • 50fs typical/ 80fs maximum RMS jitter at 312.5MHz
    • 60fs typical/ 90fs maximum RMS jitter at 156.25MHz
  • One high-performance Digital Phase-Locked Loop (DPLL) paired with two Analog Phase-Locked Loops (APLLs):
    • 1mHz to 4kHz programmable DPLL loop bandwidth
    • < 1ppt per step DCO adjustment for IEEE 1588 PTP clock steering
  • Two differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • Eight differential outputs with programmable AC-LVPECL, AC-CML, AC-LVDS, HSCL, and 1.8V LVCMOS output formats.
    • 1Hz (1PPS) to 1250MHz output frequency
    • PCIe Gen 1 to 6 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • 3.3V core supply and 1.8V, 2.5V, or 3.3V output supply
  • –40°C to +85°C operating temperature

The LMK05318B is high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of Ethernet-based networking applications.

The device integrates one DPLL and two APLLs to provide hitless switching and jitter attenuation using the programmable loop bandwidths (LBWs) with one external loop filter capacitor to maximize the flexibility and ease of use.

APLL1 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in VCO1 and can generate 312.5MHz output clocks with 50fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 features a conventional LC VCO to provide options for a second frequency and/or synchronization domain.

The integrated EEPROM can be used for custom system configurations on start-up. Internal LDO regulators provide excellent power supply noise rejection (PSNR) to reduce the cost and complexity of the power delivery network.

The LMK05318B is high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of Ethernet-based networking applications.

The device integrates one DPLL and two APLLs to provide hitless switching and jitter attenuation using the programmable loop bandwidths (LBWs) with one external loop filter capacitor to maximize the flexibility and ease of use.

APLL1 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in VCO1 and can generate 312.5MHz output clocks with 50fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 features a conventional LC VCO to provide options for a second frequency and/or synchronization domain.

The integrated EEPROM can be used for custom system configurations on start-up. Internal LDO regulators provide excellent power supply noise rejection (PSNR) to reduce the cost and complexity of the power delivery network.
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重要文件 類型 標題 格式選項 日期
* Data sheet LMK05318B 1-DPLL 2-APLL 2-IN 8-OUT Network Synchronizer With BAW VCO for Ethernet-Based Networking Applications datasheet (Rev. C) PDF | HTML 2025年 12月 10日
Application note Termination Guidelines for Differential and Single-Ended Signals PDF | HTML 2025年 12月 10日
Application note The Debug Guide for Network Synchronizers (Digital and Analog Phase-Locked Loops) PDF | HTML 2025年 11月 21日
User guide LMK05318B Register Maps User's Guide (Rev. E) PDF | HTML 2025年 11月 20日
Certificate LMK05318BEVM EU Declaration of Conformity (DoC) 2020年 6月 3日
Application note ITU-T G.8262 compliance test results for the LMK05318 (Rev. A) 2019年 2月 22日
Application note Supported synchronization modes for TI network synchronizers (Rev. A) 2019年 2月 22日
Application note Understanding clocking needs for high-speed 56G PAM-4 serial links (Rev. A) 2019年 2月 22日
White paper TI BAW technology enables ultra-low jitter clocks for high-speed networks 2019年 2月 17日
Application note How to use the LMK05318 as a jitter cleaner 2019年 1月 16日

設計與開發

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開發板

LMK05318BEVM — 網路同步器時鐘評估模組

這是適用於 LMK05318B 網路同步器時鐘裝置的評估模組 (EVM)。
EVM 可做為靈活的同步時鐘來源使用，以進行快速評估、合規測試和系統原型設計。SMA 連接埠提供對 LMK05318B 時鐘輸入和輸出的存取，以介接 50-Ω 測試設備。包含板載 XO 選項，但可以使用各種 XO/TCXO/OCXO 封裝選項重做，或繞過其他選項以使用外部 SMA 輸入。EVM 提供 USB 介面，可存取 I2C/SPI 匯流排和 LMK05318B 的控制針腳。TICS PRO 軟體 GUI 可用於編程 LMK05318B 的暫存器和 EEPROM，以儲存自訂的啟動時鐘設定。

使用指南: PDF
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TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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LMK05318 IBIS Model

SNAM226.ZIP (137 KB) - IBIS Model
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PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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