LMK3H0102
- Integrated BAW resonator, no need for external reference
- Flexible frequency generation:
- Two channel dividers: up to three unique output frequencies from 2.5MHz to 400MHz
- LVCMOS outputs supported up to 200MHz: 1.8V, 2.5V, or 3.3V
- Combination of AC-LVDS, DC-LVDS, LP-HCSL, and LVCMOS on OUT0 and OUT1 pins
- Additional LVCMOS output for generation of up to 5 LVCMOS clocks
- Total output frequency stability: ±25ppm
- 2 functional modes: I2C or preprogrammed
OTP
- Fully configurable I2C address
- PCIe Gen 1 to Gen 7 compliant: Common Clock with or without SSC, SRNS, and SRIS
- Very low PCIe jitter with SSC:
- PCIe Gen 3 Common Clock jitter: 135.3fs maximum (PCIe limit is 1ps)
- PCIe Gen 4 Common Clock jitter: 135.3fs maximum (PCIe limit is 500fs)
- PCIe Gen 5 Common Clock jitter: 57.5fs maximum (PCIe limit is 150fs)
- PCIe Gen 6 Common Clock jitter: 34.5fs maximum (PCIe limit is 100fs)
- PCIe Gen 7 Common Clock jitter: 29.6fs maximum (PCIe limit is 67fs)
- Programmable SSC modulation depth
- Preprogrammed: –0.1%, –0.25%, –0.3%, and –0.5% down spread at 200MHz FOD frequency
- Register programmable: –0.1% to –3% down spread or ±0.05% to ±1.5% center spread
- 1.8V to 3.3V supply voltage
- Internal LDOs with –93.1dBc PSNR at 500kHz switching noise for LP-HCSL outputs
- Start-up time: <1.5ms
- Output-to-output skew: <50ps
- Fail-safe digital input pins
The LMK3H0102 is a 2-output PCIe Gen 1 to Gen 7 compliant reference-less clock generator with Spread Spectrum Clocking (SSC) support. The part is based on TI proprietary Bulk Acoustic Wave (BAW) technology and provides ±25ppm clock outputs without any crystal or external clock reference. The device can provide two SSC clocks, two non-SSC clocks, or one SSC clock and one non-SSC clock at the same time. The device meets the full PCIe compliance from Gen 1 to Gen 7, including Common Clock with or without SSC, Separate Reference No Spread (SRNS), and Separate Reference Independent Spread (SRIS).
The device can be easily configured through either pins or I2C interface. An external DC/DC can be used to power the device. Refer to Power Supply Recommendations for detailed guidelines on power supply filtering and sourcing from DC/DC.
For OTP default settings for each LMK3H0102Axxx configuration, refer to the LMK3H0102 Configuration Guide.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK3H0102 Reference-Less 2-Differential or 5-Single-Ended Output PCIe Gen 1-7 Compliant Programmable BAW Clock Generator datasheet (Rev. E) | PDF | HTML | 2025/10/24 | ||
| 應用說明 | EMI Reduction Strategies With Clocking Devices | PDF | HTML | 2025/4/21 | |||
| 使用指南 | LMK3H0102 Configuration Guide | PDF | HTML | 2024/11/1 | |||
| 應用說明 | Clocking for PCIe Applications | PDF | HTML | 2023/11/28 | |||
| 白皮書 | The Importance of Clocks in Data Centers | PDF | HTML | 2023/11/21 | |||
| 應用說明 | LMK3H0102 PCI Express Compliance Report | PDF | HTML | 2023/11/14 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
LMK3H0102EVM — LMK3H0102 評估模組
TICSPRO2-GUI — 用於時脈裝置的編程序列產生和 EVM 編程工具
德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
德州儀器 (TI) 的時鐘及合成器 (TICS) 專業級軟體用於編程具有以下前置字元的產品編號的評估模組 (EVM)：CDC、LMK 和 LMX。這些產品包括鎖相迴路及電壓控制振盪器 (PLL+VCO)、合成器和時鐘裝置。
PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具
PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TQFN (RER) | 16 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。