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DS90UH981-Q1

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4K DSI to FPD-Link IV bridge serializer with HDCP

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Data sheet

DS90UH981-Q1

ACTIVE
Data sheet Order now

Product details

Function Serializer Color depth (bps) 30 Input compatibility DSI Output compatibility FPD-Link IV LVDS Parallel video bandwidth (per port) (max) (Gbps) 10 Serial video bandwidth (per port) (max) (Gbps) 10.4 Features CRC, Coax or STP, Flexible GPIOs, HDCP, I2C Config, Line Fault Detection, Pattern Generation, Ultra-Low Data and Control Path Latency Applications In-vehicle Infotainment (IVI) Signal conditioning Adaptive Equalizer EMI reduction LVDS Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
Function Serializer Color depth (bps) 30 Input compatibility DSI Output compatibility FPD-Link IV LVDS Parallel video bandwidth (per port) (max) (Gbps) 10 Serial video bandwidth (per port) (max) (Gbps) 10.4 Features CRC, Coax or STP, Flexible GPIOs, HDCP, I2C Config, Line Fault Detection, Pattern Generation, Ultra-Low Data and Control Path Latency Applications In-vehicle Infotainment (IVI) Signal conditioning Adaptive Equalizer EMI reduction LVDS Diagnostics BIST Rating Automotive Operating temperature range (°C) -40 to 105
VQFNP (RTD) 64 81 mm² 9 x 9
  • Single or dual port MIPI DSI receiver
    • Compliant to D-PHY v1.2 and DSI v1.3.1
    • Packed 16/18/24/30-bit RGB and 16-bit YCbCr
    • Loosely packed 18-bit RGB and 20-bit 4:2:2
    • 1 clock lane and 1-4 configurable data lanes per D-PHY Port
    • Up to 2.5 Gbps/lane with skew calibration
    • Supports data lane swap and polarity inversion
    • Supports both burst and non-burst mode
    • SuperFrame Unpacking Capability
    • Suitable for 4K at 60Hz video resolution
  • FPD-Link IV interface
    • Supports 10.8/6.75/3.375Gbps per channel; Up to 21.6Gbps over dual channels
    • Coax/STP interconnect support
    • Port Splitting to enable Y-cable interfaces
  • Ultra-low latency control channel
    • Two I2C up to 1MHz (up to 3.4MHz for local bus access)
    • High speed GPIOs
  • Backwards compatible
    • Integrated HDCP v1.4 with on-chip keys
    • 720P 92x and 1080P/2K 94x product families
    • ADAS 936, 954, 960, 962, 9702, 9722 deserializers
  • Security and diagnostics
    • Voltage and temperature monitoring
    • Line Fault Detection
    • BIST and pattern generation
    • CRC and error diagnostics
    • Unique ID for counterfeit protection
    • ECC on control bits
  • Advanced link robustness and EMC control
    • Data scrambling
    • Spread spectrum clocking generation (SSCG)
  • Low power operation
    • 1.8V and 1.1V dual power supply
  • AEC-Q100 qualified for automotive applications
    • AEC-Q100 grade-level 2: −40℃ to +105℃
    • 64 pin QFN Wettable flanks 9mm x 9mm
    • ISO 10605 and IEC 61000-4-2 ESD compliant
  • Single or dual port MIPI DSI receiver
    • Compliant to D-PHY v1.2 and DSI v1.3.1
    • Packed 16/18/24/30-bit RGB and 16-bit YCbCr
    • Loosely packed 18-bit RGB and 20-bit 4:2:2
    • 1 clock lane and 1-4 configurable data lanes per D-PHY Port
    • Up to 2.5 Gbps/lane with skew calibration
    • Supports data lane swap and polarity inversion
    • Supports both burst and non-burst mode
    • SuperFrame Unpacking Capability
    • Suitable for 4K at 60Hz video resolution
  • FPD-Link IV interface
    • Supports 10.8/6.75/3.375Gbps per channel; Up to 21.6Gbps over dual channels
    • Coax/STP interconnect support
    • Port Splitting to enable Y-cable interfaces
  • Ultra-low latency control channel
    • Two I2C up to 1MHz (up to 3.4MHz for local bus access)
    • High speed GPIOs
  • Backwards compatible
    • Integrated HDCP v1.4 with on-chip keys
    • 720P 92x and 1080P/2K 94x product families
    • ADAS 936, 954, 960, 962, 9702, 9722 deserializers
  • Security and diagnostics
    • Voltage and temperature monitoring
    • Line Fault Detection
    • BIST and pattern generation
    • CRC and error diagnostics
    • Unique ID for counterfeit protection
    • ECC on control bits
  • Advanced link robustness and EMC control
    • Data scrambling
    • Spread spectrum clocking generation (SSCG)
  • Low power operation
    • 1.8V and 1.1V dual power supply
  • AEC-Q100 qualified for automotive applications
    • AEC-Q100 grade-level 2: −40℃ to +105℃
    • 64 pin QFN Wettable flanks 9mm x 9mm
    • ISO 10605 and IEC 61000-4-2 ESD compliant

DS90UH981-Q1 is a MIPI DSI to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UH981-Q1 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link as well as HDCP v1.4 support when paired with an HDCP-capable deserializer. In ADAS compatible mode, the device is interoperable with 936, 95x, 96x & 97x deserializers supporting resolutions up to 8MP+/40fps.

DS90UH981-Q1 is a MIPI DSI to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UH981-Q1 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link as well as HDCP v1.4 support when paired with an HDCP-capable deserializer. In ADAS compatible mode, the device is interoperable with 936, 95x, 96x & 97x deserializers supporting resolutions up to 8MP+/40fps.

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* Data sheet DS90UH981-Q1 4K DSI to FPD-Link IV Bridge Serializer With HDCP datasheet PDF | HTML 22 Feb 2024

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Evaluation board

DS90UH981-Q1EVM — DS90UH981-Q1 DSI to FPD-Link IV bridge serializer evaluation module

The DS90Ux981-Q1EVM is an evaluation module for evaluating the DS90Ux981-Q1 MIPI DSI to FPD-Link IV serializer.  The DS90Ux981-Q1 supports ultra-high-definition resolutions including 4K with 30 bits per pixel at 60 Hz. The 2 MIPI DSI port input is compatible with MIPI DSI v1.3.1 and DPHY v1.2 (...)
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Evaluation board

DS90UH981-Q1MEVM — DS90UH981-Q1 DSI to FPD-Link IV bridge serializer evaluation module

The DS90Ux981-Q1MEVM is an evaluation module for evaluating the DS90Ux981-Q1 MIPI DSI to FPD-Link IV serializer.  The DS90Ux981-Q1 supports ultra-high-definition resolutions including 4K with 30 bits per pixel at 60 Hz. The 2 MIPI DSI port input is compatible with MIPI DSI v1.3.1 and DPHY (...)
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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