10-MHz to 100-MHz 10/12-bit FPD-Link III deserializer



Product details


Function Deserializer Color depth (bpp) 12 Input compatibility FPD-Link III LVDS Pixel clock frequency (Max) (MHz) 100 Output compatibility LVCMOS Features 2:1 input multiplexer, CRC, I2C Config, 4 GPIO, Pattern Generation, Coax or STP Signal conditioning Adaptive Equalizer EMI reduction LVDS, SSCG, Staggered Outputs Diagnostics BIST Operating temperature range (C) -40 to 105 open-in-new Find other FPD-Link SerDes

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other FPD-Link SerDes


  • 10-MHz to 100-MHz Input Pixel Clock Support
  • Single Differential Pair Interconnect
  • Programmable Data Payload:
    • 10-bit Payload up to 100 MHz
    • 12-bit Payload up to 75 MHz
  • Continuous Low Latency Bidirectional Control
    Interface Channel With I2C Support at 400 kHz
  • 2:1 Multiplexer to Choose Between Two Input
  • Embedded Clock With DC-Balanced Coding to
    Support AC-Coupled Interconnects
  • Capable of Driving up to 25 Meters Shielded
  • Receive Equalizer Automatically Adapts for
    Changes in Cable Loss
  • Four Dedicated General-Purpose Input/Output
    Pins (GPIO) Available on Both Serializer and
  • LOCK Output Reporting Pin and AT-SPEED BIST
    Diagnosis Feature to Validate Link Integrity
  • 1.8-V, 2.8-V or 3.3-V Compatible Parallel Inputs
    on Serializer
  • Single Power Supply at 1.8 V
  • ISO 10605 and IEC 61000-4-2 ESD Compliant
  • Automotive-Grade Product: AEC-Q100 Grade 2
  • Temperature Range −40°C to +105°C
  • Small Serializer Footprint (5 mm × 5 mm)
  • EMI/EMC Mitigation on Deserializer
    • Programmable Spread Spectrum (SSCG)
    • Receiver Staggered Outputs
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The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus.

There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period.

Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package.

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Technical documentation

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Type Title Date
* Data sheet DS90UB91xQ-Q1 10- to 100-MHz, 10- and 12-Bit DC-Balanced FPD-Link III Serializer and Deserializer With Bidirectional Control Channel datasheet (Rev. D) Jul. 31, 2015
Technical article How to choose a power supply for an automotive camera module Sep. 17, 2020
Application note Migrating DS90UB914A-Q1 Designs to DS90UB934-Q1 for Automotive ADAS Systems (Rev. A) Feb. 05, 2018
Application note I2C Communication over DS90UB913/4 FPD Link-III with BCC Apr. 22, 2013
User guide DS90UB913Q Serializer and DS90UB914Q Deserializer Evaluation Kit Aug. 08, 2012

Design & development

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Software development

SNLC048D.ZIP (24784 KB)
Analog LaunchPad™ software
ALP Analog LaunchPad (ALP) software is an interactive graphical user interface (GUI) software platform to evaluate TI FPD-Link™ serializers and deserializers (SerDes). ALP software enables device- and system-level evaluation with powerful built-in features, including:
  • Local and remote device access
  • Device (...)

Design tools & simulation

SNLM123.ZIP (147 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

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