SPRUJB3C March 2024 – November 2025 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
CBASS arbitrates the transaction based on priority from high to low. If the transactions going to the same end point have the same priority, then the CBASS uses round robin method for these transactions.
In the CBASS with parallel paths, orderID is used to determine how the transactions are forwarded to those parallel paths. The parallel paths are defined as two target interfaces with the exact same memory map assignment.
By default, all the target interfaces have a certain address assigned and CBASS routes the transactions based on this address. However, some of the special target interfaces can be routed through a different mechanism using the ASEL signal, such as MPU A53SS’s ACP interface and PCIe target interfaces.
By default, the majority of the transactions default to the lowest priority level, ASEL value to zero and orderID to zero. The transactions from BCDMA and pktDMA have those attributes as part of the DMA configuration. ASEL value is part of the address information passed to the DMA engine. It is normally specified in descriptors such as host packet descriptor and host buffer descriptor for pktDMA, and Transfer Request (TR) packet descriptor for BCDMA. The priority and orderID information can be configured through each DMA channel’s priority control register.
For the rest of the initiators, the CBASS IP provides QoS block to allow the user to program the transaction’s attributes such as priority level, ASEL coding and orderID.
The QoS block programming is through CBASS’s qos_regs region. Each initiator, except the BCDMA, pktDMA, and debugss, has an MMR to allow the user to set the priority, ASEL, and orderID value. There is another exception on priority setting. The display IP implements dynamic priority schedule based on the FIFO threshold. The QoS block inside CBASS does not have the ability to overwrite the priority value coming from the display IP.
Each QoS block has one 4B MAP register per channel that allows the user to program ASEL, orderID, and priority. The first MAP register is at offset 0x100 and the MAP register for channel X is located at offset 0x100+400x. See QoS Block MMR.
For any write to address range 0x4500_0000 to 0x45FF_FFFF, it is recommended to read back the value after the write to make sure the write landed. The registers in this regions are mainly for firewall configuration, ISC/DMA credential configuration, QoS MMR configuration.
On QoS MMR configuration, in order to configure certain transaction to be the highest priority, the priority field needs to be set to zero for that transaction. In order to make sure that priority field is indeed to set to zero, the following sequence should be followed: