SPRUJB3 User guide

SPRUJB3C March 2024 – November 2025 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

4.15.1.1 DCC Integration

Table 4-392 DCC Module Allocations

Instance	MAIN	MCU
DCC0	✓
DCC1	✓
DCC2	✓
DCC3	✓
DCC4	✓
DCC5	✓
DCC6	✓
DCC7	✓
DCC8	✓
MCU_DCC0		✓
MCU_DCC1		✓

Table 4-393 Integration Attributes for DCC

Module Instance	Power Sleep Controller	Power Domain	Module Domain	Default	Controllable
DCC0	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
DCC1	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
DCC2	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
DCC3	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
DCC4	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
DCC5	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
DCC6	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
DCC7	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
DCC8	PSC0	GP_CORE	LPSC_main_alwayson	ON	NO
MCU_DCC0	WKUP_PSC0	GP_core_CTL_MCU	LPSC_mcu_alwayson	ON	NO
MCU_DCC1	WKUP_PSC0	GP_core_CTL_MCU	LPSC_mcu_alwayson	ON	NO

Table 4-394 Clock Integration for DCC

Module Instance	Module Clock Input	Source Clock	Source Control Register	Description
DCC0	DCC_CLKSRC0_CLK	MAIN_PLL0_HSDIV1_CLKOUT		counter1 clock source
DCC0	DCC_CLKSRC1_CLK	MAIN_PLL0_HSDIV2_CLKOUT		counter1 clock source
DCC0	DCC_CLKSRC2_CLK	MAIN_PLL0_HSDIV3_CLKOUT		counter1 clock source
DCC0	DCC_CLKSRC3_CLK	MAIN_PLL0_HSDIV4_CLKOUT		counter1 clock source
DCC0	DCC_CLKSRC4_CLK	CLK_12M_RC		counter1 clock source
DCC0	DCC_CLKSRC4_CLK	HFOSC0 (INSTANCE)		counter1 clock source
DCC0	DCC_CLKSRC5_CLK	EXT_REFCLK1		counter1 clock source
DCC0	DCC_CLKSRC6_CLK	MAIN_SYSCLK0		counter1 clock source
DCC0	DCC_CLKSRC7_CLK	MAIN_PLL2_HSDIV8_CLKOUT		counter1 clock source
DCC0	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC0	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC0	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC0	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC0	DCC_INPUT10_CLK	MAIN_SYSCLK0/2		secondary oscillator clock
DCC0	FICLK	MAIN_SYSCLK0/4		functional and interface clock
DCC1	DCC_CLKSRC0_CLK	MAIN_PLL0_HSDIV5_CLKOUT		counter1 clock source
DCC1	DCC_CLKSRC1_CLK	MAIN_PLL0_HSDIV6_CLKOUT		counter1 clock source
DCC1	DCC_CLKSRC2_CLK	MAIN_PLL0_HSDIV7_CLKOUT		counter1 clock source
DCC1	DCC_CLKSRC3_CLK	MAIN_PLL1_HSDIV1_CLKOUT		counter1 clock source
DCC1	DCC_CLKSRC4_CLK	MAIN_PLL15_HSDIV2_CLKOUT/4		counter1 clock source
DCC1	DCC_CLKSRC5_CLK	MAIN_PLL1_HSDIV0_CLKOUT		counter1 clock source
DCC1	DCC_CLKSRC6_CLK	CLK_12M_RC		counter1 clock source
DCC1	DCC_CLKSRC7_CLK	MAIN_PLL1_HSDIV2_CLKOUT		counter1 clock source
DCC1	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC1	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC1	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC1	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC1	DCC_INPUT10_CLK	MAIN_SYSCLK0/4		secondary oscillator clock
DCC1	FICLK	MAIN_SYSCLK0/4		functional and interface clock
DCC2	DCC_CLKSRC0_CLK	MAIN_PLL1_HSDIV3_CLKOUT		counter1 clock source
DCC2	DCC_CLKSRC1_CLK	MAIN_PLL15_HSDIV0_CLKOUT		counter1 clock source
DCC2	DCC_CLKSRC2_CLK	MAIN_PLL1_HSDIV5_CLKOUT		counter1 clock source
DCC2	DCC_CLKSRC3_CLK	MAIN_PLL1_HSDIV6_CLKOUT		counter1 clock source
DCC2	DCC_CLKSRC4_CLK	MAIN_PLL5_HSDIV1_CLKOUT		counter1 clock source
DCC2	DCC_CLKSRC5_CLK	MAIN_PLL15_HSDIV1_CLKOUT		counter1 clock source
DCC2	DCC_CLKSRC6_CLK	MAIN_PLL2_HSDIV2_CLKOUT		counter1 clock source
DCC2	DCC_CLKSRC7_CLK	RMII2_REF_CLK (PIN)		counter1 clock source
DCC2	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC2	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC2	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC2	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC2	DCC_INPUT10_CLK	MAIN_SYSCLK0/4		secondary oscillator clock
DCC2	FICLK	MAIN_SYSCLK0/4		functional and interface clock
DCC3	DCC_CLKSRC0_CLK	MAIN_PLL1_HSDIV0_CLKOUT		counter1 clock source
DCC3	DCC_CLKSRC1_CLK	MAIN_PLL2_HSDIV5_CLKOUT		counter1 clock source
DCC3	DCC_CLKSRC2_CLK	C7X256V0_CLK (INSTANCE)		counter1 clock source
DCC3	DCC_CLKSRC3_CLK	MAIN_PLL2_HSDIV7_CLKOUT		counter1 clock source
DCC3	DCC_CLKSRC4_CLK	MAIN_PLL2_HSDIV6_CLKOUT		counter1 clock source
DCC3	DCC_CLKSRC5_CLK	MAIN_PLL2_HSDIV9_CLKOUT		counter1 clock source
DCC3	DCC_CLKSRC6_CLK	A53SS0 (INSTANCE)/4		counter1 clock source
DCC3	DCC_CLKSRC7_CLK	DDR32SS0 (INSTANCE)		counter1 clock source
DCC3	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC3	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC3	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC3	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC3	DCC_INPUT10_CLK	MAIN_SYSCLK0/4		secondary oscillator clock
DCC3	FICLK	MAIN_SYSCLK0/4		functional and interface clock
DCC4	DCC_CLKSRC1_CLK	CP_GEMAC_CPTS_REF_CLK		counter1 clock source
DCC4	DCC_CLKSRC2_CLK	AUDIO_EXT_REFCLK1 (PIN)		counter1 clock source
DCC4	DCC_CLKSRC3_CLK	DPHY_RX0 (INSTANCE)		counter1 clock source
DCC4	DCC_CLKSRC4_CLK	MCU_EXT_REFCLK0		counter1 clock source
DCC4	DCC_CLKSRC5_CLK	RMII1_REF_CLK (PIN)/4		counter1 clock source
DCC4	DCC_CLKSRC7_CLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	counter1 clock source
DCC4	DCC_CLKSRC7_CLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	counter1 clock source
DCC4	DCC_CLKSRC7_CLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	counter1 clock source
DCC4	DCC_CLKSRC7_CLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	counter1 clock source
DCC4	DCC_CLKSRC7_CLK	LFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	counter1 clock source
DCC4	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC4	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC4	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC4	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC4	DCC_INPUT10_CLK	MAIN_SYSCLK0/2		secondary oscillator clock
DCC4	FICLK	MAIN_SYSCLK0/4		functional and interface clock
DCC5	DCC_CLKSRC0_CLK	MAIN_PLL0_HSDIV8_CLKOUT		counter1 clock source
DCC5	DCC_CLKSRC1_CLK	AUDIO_EXT_REFCLK2 (PIN)		counter1 clock source
DCC5	DCC_CLKSRC2_CLK	MAIN_PLL2_HSDIV1_CLKOUT		counter1 clock source
DCC5	DCC_CLKSRC3_CLK	MAIN_PLL2_HSDIV3_CLKOUT		counter1 clock source
DCC5	DCC_CLKSRC4_CLK	MAIN_PLL2_HSDIV4_CLKOUT		counter1 clock source
DCC5	DCC_CLKSRC5_CLK	MAIN_PLL5_HSDIV0_CLKOUT/2		counter1 clock source
DCC5	DCC_CLKSRC6_CLK	MAIN_PLL17_HSDIV0_CLKOUT		counter1 clock source
DCC5	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC5	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC5	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC5	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC5	DCC_INPUT10_CLK	MAIN_SYSCLK0		secondary oscillator clock
DCC5	FICLK	MAIN_SYSCLK0/4		functional and interface clock
DCC6	DCC_CLKSRC0_CLK	VOUT0_EXTPCLKIN (PIN)		counter1 clock source
DCC6	DCC_CLKSRC1_CLK	MCASP0_ACLKX (PIN)		counter1 clock source
DCC6	DCC_CLKSRC2_CLK	MCASP0_ACLKR (PIN)		counter1 clock source
DCC6	DCC_CLKSRC3_CLK	MCASP1_ACLKX (PIN)		counter1 clock source
DCC6	DCC_CLKSRC4_CLK	MCASP1_ACLKR (PIN)		counter1 clock source
DCC6	DCC_CLKSRC5_CLK	MCASP2_ACLKX (PIN)		counter1 clock source
DCC6	DCC_CLKSRC6_CLK	MCASP2_ACLKR (PIN)		counter1 clock source
DCC6	DCC_CLKSRC7_CLK	AUDIO_EXT_REFCLK0 (PIN)		counter1 clock source
DCC6	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC6	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC6	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC6	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC6	DCC_INPUT10_CLK	MAIN_SYSCLK0		secondary oscillator clock
DCC6	FICLK	MAIN_SYSCLK0/4		functional and interface clock
DCC7	DCC_CLKSRC0_CLK	MAIN_PLL5_HSDIV2_CLKOUT/2		counter1 clock source
DCC7	DCC_CLKSRC1_CLK	GPU0 (INSTANCE)/4		counter1 clock source
DCC7	DCC_CLKSRC2_CLK	MAIN_PLL16_HSDIV0_CLKOUT/8		counter1 clock source
DCC7	DCC_CLKSRC3_CLK	DPHY_RX1 (INSTANCE)		counter1 clock source
DCC7	DCC_CLKSRC4_CLK	C7X256V1_CLK (INSTANCE)		counter1 clock source
DCC7	DCC_CLKSRC5_CLK	MAIN_PLL0_HSDIV9_CLKOUT		counter1 clock source
DCC7	DCC_CLKSRC6_CLK	MAIN_PLL1_HSDIV4_CLKOUT		counter1 clock source
DCC7	DCC_CLKSRC7_CLK	MAIN_PLL2_HSDIV0_CLKOUT		counter1 clock source
DCC7	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC7	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC7	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC7	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC7	DCC_INPUT10_CLK	MAIN_SYSCLK0		secondary oscillator clock
DCC7	FICLK	MAIN_SYSCLK0/4		functional and interface clock
DCC8	DCC_CLKSRC0_CLK	MAIN_PLL15_HSDIV3_CLKOUT/4		counter1 clock source
DCC8	DCC_CLKSRC1_CLK	MAIN_PLL18_HSDIV0_CLKOUT/2		counter1 clock source
DCC8	DCC_CLKSRC2_CLK	DPHY_RX2 (INSTANCE)		counter1 clock source
DCC8	DCC_CLKSRC3_CLK	DPHY_RX3 (INSTANCE)		counter1 clock source
DCC8	DCC_CLKSRC4_CLK	MCASP3_ACLKX (PIN)		counter1 clock source
DCC8	DCC_CLKSRC5_CLK	MCASP3_ACLKR (PIN)		counter1 clock source
DCC8	DCC_CLKSRC6_CLK	MCASP4_ACLKX (PIN)		counter1 clock source
DCC8	DCC_CLKSRC7_CLK	MCASP4_ACLKR (PIN)		counter1 clock source
DCC8	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
DCC8	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
DCC8	DCC_INPUT01_CLK	EXT_REFCLK1		primary oscillator clock
DCC8	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
DCC8	DCC_INPUT10_CLK	MAIN_SYSCLK0		secondary oscillator clock
DCC8	FICLK	MAIN_SYSCLK0/4		functional and interface clock
MCU_DCC0	DCC_CLKSRC0_CLK	MCU_PLL0_HSDIV0_CLKOUT		counter1 clock source
MCU_DCC0	DCC_CLKSRC1_CLK	MCU_PLL0_HSDIV1_CLKOUT		counter1 clock source
MCU_DCC0	DCC_CLKSRC2_CLK	MCU_PLL0_HSDIV2_CLKOUT		counter1 clock source
MCU_DCC0	DCC_CLKSRC3_CLK	MCU_PLL0_HSDIV3_CLKOUT/4		counter1 clock source
MCU_DCC0	DCC_CLKSRC4_CLK	MCU_PLL0_HSDIV4_CLKOUT		counter1 clock source
MCU_DCC0	DCC_CLKSRC5_CLK	CLK_32K_RC		counter1 clock source
MCU_DCC0	DCC_CLKSRC6_CLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	counter1 clock source
MCU_DCC0	DCC_CLKSRC6_CLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	counter1 clock source
MCU_DCC0	DCC_CLKSRC6_CLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	counter1 clock source
MCU_DCC0	DCC_CLKSRC6_CLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	counter1 clock source
MCU_DCC0	DCC_CLKSRC6_CLK	LFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	counter1 clock source
MCU_DCC0	DCC_CLKSRC7_CLK	MCU_EXT_REFCLK0		counter1 clock source
MCU_DCC0	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
MCU_DCC0	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
MCU_DCC0	DCC_INPUT01_CLK	CLK_32K_RC		primary oscillator clock
MCU_DCC0	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
MCU_DCC0	DCC_INPUT10_CLK	MCU_SYSCLK0/2		secondary oscillator clock
MCU_DCC0	FICLK	MCU_SYSCLK0/4		functional and interface clock
MCU_DCC1	DCC_CLKSRC0_CLK	MCU_PLL0_HSDIV5_CLKOUT		counter1 clock source
MCU_DCC1	DCC_CLKSRC1_CLK	MCU_PLL0_HSDIV6_CLKOUT		counter1 clock source
MCU_DCC1	DCC_CLKSRC5_CLK	CLK_32K_RC		counter1 clock source
MCU_DCC1	DCC_CLKSRC6_CLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=0	counter1 clock source
MCU_DCC1	DCC_CLKSRC6_CLK	CLK_12M_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	counter1 clock source
MCU_DCC1	DCC_CLKSRC6_CLK	HFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=1	counter1 clock source
MCU_DCC1	DCC_CLKSRC6_CLK	CLK_32K_RC	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=2	counter1 clock source
MCU_DCC1	DCC_CLKSRC6_CLK	LFOSC0 (INSTANCE)	MCU_CTRL_MMR_CFG0_DEVICE_CLKOUT_32K_CTRL[1:0]=3	counter1 clock source
MCU_DCC1	DCC_CLKSRC7_CLK	MCU_EXT_REFCLK0		counter1 clock source
MCU_DCC1	DCC_INPUT00_CLK	CLK_12M_RC		primary oscillator clock
MCU_DCC1	DCC_INPUT00_CLK	HFOSC0 (INSTANCE)		primary oscillator clock
MCU_DCC1	DCC_INPUT01_CLK	CLK_32K_RC		primary oscillator clock
MCU_DCC1	DCC_INPUT02_CLK	CLK_12M_RC		primary oscillator clock
MCU_DCC1	DCC_INPUT10_CLK	MCU_SYSCLK0/2		secondary oscillator clock
MCU_DCC1	FICLK	MCU_SYSCLK0/4		functional and interface clock

Table 4-395 Reset Integration for DCC

Module Instance	Source	Description
DCC0	PSC0	DCC0 reset
DCC1	PSC0	DCC1 reset
DCC2	PSC0	DCC2 reset
DCC3	PSC0	DCC3 reset
DCC4	PSC0	DCC4 reset
DCC5	PSC0	DCC5 reset
DCC6	PSC0	DCC6 reset
DCC7	PSC0	DCC7 reset
DCC8	PSC0	DCC8 reset
MCU_DCC0	WKUP_PSC0	MCU_DCC0 reset
MCU_DCC1	WKUP_PSC0	MCU_DCC1 reset

Table 4-396 Hardware Requests for DCC

Module Instance	Module Interrupt Signal	Destination Interrupt Input	Destination	Description	Type
DCC0	DCC0_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC0 interrupt request	level
DCC0	DCC0_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC0 interrupt request	level
DCC0	DCC0_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC0 interrupt request	level
DCC0	DCC0_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC0 interrupt request	level
DCC0	DCC0_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC0 interrupt request	level
DCC0	DCC0_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC0 interrupt request	level
DCC0	DCC0_intr_err_level_0	ESM0_esm_lvl_event_112	ESM0	DCC0 interrupt request	level
DCC1	DCC1_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC1 interrupt request	level
DCC1	DCC1_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC1 interrupt request	level
DCC1	DCC1_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC1 interrupt request	level
DCC1	DCC1_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC1 interrupt request	level
DCC1	DCC1_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC1 interrupt request	level
DCC1	DCC1_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC1 interrupt request	level
DCC1	DCC1_intr_err_level_0	ESM0_esm_lvl_event_113	ESM0	DCC1 interrupt request	level
DCC2	DCC2_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC2 interrupt request	level
DCC2	DCC2_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC2 interrupt request	level
DCC2	DCC2_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC2 interrupt request	level
DCC2	DCC2_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC2 interrupt request	level
DCC2	DCC2_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC2 interrupt request	level
DCC2	DCC2_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC2 interrupt request	level
DCC2	DCC2_intr_err_level_0	ESM0_esm_lvl_event_114	ESM0	DCC2 interrupt request	level
DCC3	DCC3_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC3 interrupt request	level
DCC3	DCC3_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC3 interrupt request	level
DCC3	DCC3_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC3 interrupt request	level
DCC3	DCC3_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC3 interrupt request	level
DCC3	DCC3_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC3 interrupt request	level
DCC3	DCC3_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC3 interrupt request	level
DCC3	DCC3_intr_err_level_0	ESM0_esm_lvl_event_115	ESM0	DCC3 interrupt request	level
DCC4	DCC4_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC4 interrupt request	level
DCC4	DCC4_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC4 interrupt request	level
DCC4	DCC4_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC4 interrupt request	level
DCC4	DCC4_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC4 interrupt request	level
DCC4	DCC4_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC4 interrupt request	level
DCC4	DCC4_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC4 interrupt request	level
DCC4	DCC4_intr_err_level_0	ESM0_esm_lvl_event_116	ESM0	DCC4 interrupt request	level
DCC5	DCC5_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC5 interrupt request	level
DCC5	DCC5_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC5 interrupt request	level
DCC5	DCC5_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC5 interrupt request	level
DCC5	DCC5_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC5 interrupt request	level
DCC5	DCC5_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC5 interrupt request	level
DCC5	DCC5_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC5 interrupt request	level
DCC5	DCC5_intr_err_level_0	ESM0_esm_lvl_event_117	ESM0	DCC5 interrupt request	level
DCC6	DCC6_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC6 interrupt request	level
DCC6	DCC6_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC6 interrupt request	level
DCC6	DCC6_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC6 interrupt request	level
DCC6	DCC6_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC6 interrupt request	level
DCC6	DCC6_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC6 interrupt request	level
DCC6	DCC6_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC6 interrupt request	level
DCC6	DCC6_intr_err_level_0	ESM0_esm_lvl_event_79	ESM0	DCC6 interrupt request	level
DCC7	DCC7_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC7 interrupt request	level
DCC7	DCC7_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC7 interrupt request	level
DCC7	DCC7_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC7 interrupt request	level
DCC7	DCC7_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC7 interrupt request	level
DCC7	DCC7_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC7 interrupt request	level
DCC7	DCC7_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC7 interrupt request	level
DCC7	DCC7_intr_err_level_0	ESM0_esm_lvl_event_73	ESM0	DCC7 interrupt request	level
DCC8	DCC8_intr_done_level_0	GICSS0_spi_128	GICSS0	DCC8 interrupt request	level
DCC8	DCC8_intr_done_level_0	R5FSS0_CORE0_intr_109	R5FSS0_CORE0	DCC8 interrupt request	level
DCC8	DCC8_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_109	WKUP_R5FSS0_CORE0	DCC8 interrupt request	level
DCC8	DCC8_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_109	MCU_R5FSS0_CORE0	DCC8 interrupt request	level
DCC8	DCC8_intr_done_level_0	C7X256V0_CLEC_gic_spi_128	C7X256V0_CLEC	DCC8 interrupt request	level
DCC8	DCC8_intr_done_level_0	C7X256V1_CLEC_gic_spi_128	C7X256V1_CLEC	DCC8 interrupt request	level
DCC8	DCC8_intr_err_level_0	ESM0_esm_lvl_event_223	ESM0	DCC8 interrupt request	level
MCU_DCC0	MCU_DCC0_intr_done_level_0	R5FSS0_CORE0_intr_108	R5FSS0_CORE0	MCU_DCC0 interrupt request	level
MCU_DCC0	MCU_DCC0_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_108	WKUP_R5FSS0_CORE0	MCU_DCC0 interrupt request	level
MCU_DCC0	MCU_DCC0_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_108	MCU_R5FSS0_CORE0	MCU_DCC0 interrupt request	level
MCU_DCC0	MCU_DCC0_intr_err_level_0	WKUP_ESM0_esm_lvl_event_37	WKUP_ESM0	MCU_DCC0 interrupt request	level
MCU_DCC1	MCU_DCC1_intr_done_level_0	R5FSS0_CORE0_intr_137	R5FSS0_CORE0	MCU_DCC1 interrupt request	level
MCU_DCC1	MCU_DCC1_intr_done_level_0	WKUP_R5FSS0_CORE0_intr_137	WKUP_R5FSS0_CORE0	MCU_DCC1 interrupt request	level
MCU_DCC1	MCU_DCC1_intr_done_level_0	MCU_R5FSS0_CORE0_cpu0_intr_137	MCU_R5FSS0_CORE0	MCU_DCC1 interrupt request	level
MCU_DCC1	MCU_DCC1_intr_err_level_0	WKUP_ESM0_esm_lvl_event_36	WKUP_ESM0	MCU_DCC1 interrupt request	level