SPRUJB3 User guide

SPRUJB3C March 2024 – November 2025 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1

Table 6-44 lists the basic information of the MCU PLL.

Table 6-44 Basic Information of MCU_PLL0

PLL name	Type	HSDIV Available	Input clock	Comments
MCU_PLL0	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2, HSDIV3, HSDIV4	HFOSC0_CLKOUT	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾

(1) See Figure 6-37, Generic PLL Functional Diagram for PLLTS16FFCLAFRACF2 type for overview of the PLL.

(2) See Section 6.4.5.5.2 for synthesized clock parameters.

(3) See Section 6.4.5.5.3 for clock output parameters.

Table 6-45 lists the basic information of each of the MAIN PLLs.

Table 6-45 Basic Information of MAIN Domain PLLs

PLL name	Type	HSDIV Available	Input clock	Comments
PLL0	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2, HSDIV3, HSDIV4, HSDIV5, HSDIV6, HSDIV7, HSDIV8, HSDIV9	MAIN_PLL0_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL1	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2, HSDIV3, HSDIV4, HSDIV5, HSDIV6	MAIN_PLL1_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL2	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2, HSDIV3, HSDIV4, HSDIV5, HSDIV6, HSDIV7, HSDIV8, HSDIV9	MAIN_PLL2_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL5	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1, HSDIV2	MAIN_PLL5_REFCLK	⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL6	PLLTS16FFCLAFRACF2	HSDIV0	MAIN_PLL6_REFCLK	⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL7	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1	MAIN_PLL7_REFCLK	⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL8	PLLTS16FFCLAFRACF2	HSDIV0	MAIN_PLL8_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL12	PLLTS16FFCLAFRACF2	HSDIV0	MAIN_PLL12_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL15	PLLTS16FFCLAFRACF2	HSDIV0, HSDIV1	MAIN_PLL15_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL16	PLLTS16FFCLAFRACF2	HSDIV0	MAIN_PLL16_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL17	PLLTS16FFCLAFRACF2	HSDIV0	MAIN_PLL17_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
PLL18	PLLTS16FFCLAFRACF2	HSDIV0	MAIN_PLL18_REFCLK	See ⁽¹⁾, ⁽²⁾, and ⁽³⁾

(1) See Figure 6-37, Generic PLL Functional Diagram for PLLTS16FFCLAFRACF2 type for overview of the PLL.

(2) See Section 6.4.5.5.2 for synthesized clock parameters.

(3) See Section 6.4.5.5.3 for clock output parameters.