10.5.25 ADCSSOP1 and ADCSSOP2 Registers [reset = 0x0]
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090
This register determines whether the sample from the given conversion on Sample Sequence n is saved in the Sample Sequence n FIFO or sent to the digital comparator unit. The ADCSSOP1 register controls Sample Sequencer 1 and the ADCSSOP2 register controls Sample Sequencer 2.
ADCSSOP1 is shown in Figure 10-39 and described in Table 10-33.
Return to Summary Table.
Figure 10-39 ADCSSOP1 Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
S3DCOP |
RESERVED |
S2DCOP |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
S1DCOP |
RESERVED |
S0DCOP |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 10-33 ADCSSOP1 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-13 |
RESERVED |
R |
0x0 |
|
| 12 |
S3DCOP |
R/W |
0x0 |
Sample 3 Digital Comparator Operation.
0x0 = The fourth sample is saved in Sample Sequence FIFOn.
0x1 = The fourth sample is sent to the digital comparator unit specified by the S3DCSEL bit in the ADCSSDC0n register, and the value is not written to the FIFO.
|
| 11-9 |
RESERVED |
R |
0x0 |
|
| 8 |
S2DCOP |
R/W |
0x0 |
Sample 2 Digital Comparator Operation.
Same definition as S3DCOP but used during the third sample. |
| 7-5 |
RESERVED |
R |
0x0 |
|
| 4 |
S1DCOP |
R/W |
0x0 |
Sample 1 Digital Comparator Operation.
Same definition as S3DCOP but used during the second sample. |
| 3-1 |
RESERVED |
R |
0x0 |
|
| 0 |
S0DCOP |
R/W |
0x0 |
Sample 0 Digital Comparator Operation.
Same definition as S3DCOP but used during the first sample. |