16.5.23 EPIEISC Register (Offset = 0x21C) [reset = 0x0]
EPI Error and Interrupt Status and Clear (EPIEISC)
This register is used to clear a pending error interrupt. Clearing any defined bit in the EPIEISC has no effect; setting a bit clears the error source and the raw error returns to 0. When any of bits[2:0] of this register are read as set, it indicates that the ERRRIS bit in the EPIRIS register is set and an EPI controller error is sent to the interrupt controller if the ERIM bit in the EPIIM register is set. If any of bits [2:0] are written as 1, the register bit being written to, as well as the ERRIS bit in the EPIRIS register and the ERIM bit in the EPIIM register are cleared.If the DMAWRIC or DMARDIC bit in this register is set, then the corresponding bit in the EPIRIS and EPIMIS register is cleared. Note that writing to this register and reading back immediately (pipelined by the processor) returns the old register contents. One cycle is needed between write and read.
EPIEISC is shown in Figure 16-52 and described in Table 16-36.
Return to Summary Table.
Figure 16-52 EPIEISC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DMAWRIC |
DMARDIC |
WTFULL |
RSTALL |
TOUT |
| R-0x0 |
W1C-0x0 |
W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
R/W1C-0x0 |
|
Table 16-36 EPIEISC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
DMAWRIC |
W1C |
0x0 |
Write µDMA Interrupt Clear. Writing a 1 to this bit clears the DMAWRRIS bit in the EPIRIS register and the DMAWRMIS bit in the EPIMIS register.
|
| 3 |
DMARDIC |
W1C |
0x0 |
Read µDMA Interrupt Clear. Writing a 1 to this bit clears the DMARDRIS bit in the EPIRIS register and the DMARDMIS bit in the EPIMIS register.
|
| 2 |
WTFULL |
R/W1C |
0x0 |
Write FIFO Full Error. Writing a 1 to this bit clears it, as well as the ERRRIS and ERIM bits.
0x0 = The WFERR bit is not enabled or no writes are stalled.
0x1 = The WFERR bit is enabled and a write is stalled due to the WFIFO being full.
|
| 1 |
RSTALL |
R/W1C |
0x0 |
Read Stalled Error. Writing a 1 to this bit clears it, as well as the ERRRIS and ERIM bits.
0x0 = The RSERR bit is not enabled or no pending reads are stalled.
0x1 = The RSERR bit is enabled and a pending read is stalled due to writes in the WFIFO.
|
| 0 |
TOUT |
R/W1C |
0x0 |
Timeout Error. This bit is the timeout error source.
The timeout error occurs when the XFIFO not-ready signals hold a transaction for more than the count in the MAXWAIT field (when not 0).
Writing a 1 to this bit clears it, as well as the ERRRIS and ERIM bits.
0x0 = No timeout error has occurred.
0x1 = A timeout error has occurred.
|