SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 2-49 lists the memory-mapped registers for the FPU. All register offset addresses not listed in Table 2-49 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0xD88 | CPAC | Coprocessor Access Control | Section 2.7.1 |
| 0xF34 | FPCC | Floating-Point Context Control | Section 2.7.2 |
| 0xF38 | FPCA | Floating-Point Context Address | Section 2.7.3 |
| 0xF3C | FPDSC | Floating-Point Default Status Control | Section 2.7.4 |
Complex bit access types are encoded to fit into small table cells. Table 2-50 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |