SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 25-25 lists the memory-mapped registers for the SHA/MD5 µDMA. All register offset addresses not listed in Table 25-25 should be considered as reserved locations and the register contents should not be modified. The SHA μDMA offsets are relative to the base address 0x44030000.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x10 | SHA_DMAIM | SHA DMA Interrupt Mask | Section 25.3.1 |
| 0x14 | SHA_DMARIS | SHA DMA Raw Interrupt Status | Section 25.3.2 |
| 0x18 | SHA_DMAMIS | SHA DMA Masked Interrupt Status | Section 25.3.3 |
| 0x1C | SHA_DMAIC | SHA DMA Interrupt Clear | Section 25.3.4 |
Complex bit access types are encoded to fit into small table cells. Table 25-26 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |