SPRAD21I May 2022 – September 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62D-Q1 , AM62P , AM62P-Q1
For optimizing the custom board design, the processor clock output (CLKOUT0) can be used as clock source (input) to the EPHy. CLKOUT0 is buffered internally and is intended to be connected in a point-to-point clock topology. Buffering of the CKLOUT0 (individually) is recommended before connecting to the clock input of the attached devices (EPHy). A series resistor (0Ω, adjust after testing) is recommended at the source end of the CLKOUT0 to control possible signal reflections.
EPHY using RGMII interface requires a 25MHz clock input that is not synchronous to any other signals. 25MHz clock does not have any timing requirements, but is important the EPHy does not receive any non-monotonic transitions on the clock input.
When EPHY is configured for RMII interface, clocking option depends on the EPHY configuration.
When EPHY is configured as a controller, many of the RMII EPHy use a 25MHz input clock that is not synchronous to any other signals, the 25MHz clock signal does not have any timing requirements, but is important to make sure the EPHY does not receive any non-monotonic transitions on the clock input.
The RMII EPHY provides the 50MHz clock output to the MAC. For RMII use case, the 50MHz data transfer clock is delayed (hardware delay) to the MAC relative to the EPHY. The delay shifts clock to data timing relationship which can erode the timing margin. Eroded timing margin can be a concern for some designs if the delay is large.
When EPHY is configured as a device, the MAC and the EPHY uses a 50MHz common clock that is synchronous to both transmit and receive data. The 50MHz clock is defined in the RMII specification as a common data transfer clock signal that is used by both the MAC and the EPHY, where transitions are expected to arrive simultaneously at the MAC and EPHY device pins. The common clock provides better timing margin for both transmit and receive data transfers. Important requirement is that the MAC and EPHY do not receive any non-monotonic transitions on the clock inputs. To control the clock signal integrity, the recommendation is to route the common clock signal through a single input, two-output phase aligned buffer. The recommendation is to use equal length signal traces that are half the length of the data signals for connecting the clock buffer outputs, where one clock output connects to the MAC and the other connects to the EPHY.
For RMII interface, the recommended configuration RMII Interface Typical Application (External Clock Source) is explained in the processor-specific TRM. When the RMII Interface Typical Application (Internal Clock Source) configuration is used, the recommendation is to validate performance on a board level. The recommendation is to provision for connecting an external clock for initial performance testing and comparison with internal clock.
The Ethernet performance (RGMII) is validated on the processor and the EPHY (used on the SK board) with 25MHz clock frequency.
The CLKOUT0 can be used to source a 25MHz or a 50MHz clock to processor (MAC) and EPHY. The CLKOUT0 output is available after the software configures the clock output. The CLKOUT0 configuration is not recommended when support for Ethernet boot is required. CLKOUT0 connected as EPHY clock input is likely to glitch anytime the configuration is changed.
For AM62x, AM62Ax and AM62D-Q1 processor families, WKUP_CLKOUT0 is the buffered output of MCU_OSC0_XO and is sourced after processor is reset. The clock output does not glitch after the clock begins to toggle. However, the first high or low pulse can be short because reset is released asynchronous to the MCU_OSC0 clock.
For AM62Px processor family, WKUP_CLKOUT0 is required to be configured to source the processor reference clock (MCU_OSC0_XO). The clock output does not glitch after the clock begins to toggle. However, the first high or low pulse can be short because reset is released asynchronous to the MCU_OSC0 clock.
Processor clock outputs performance is not defined in the processor-specific data sheet since the clock performance can be influenced by a number of variables unique to each custom board design. The recommendation for custom board designer is to validate timing of all peripherals by using the actual PCB delays, minimum or maximum output delay characteristics, and minimum setup and hold requirements of each device to confirm there is enough timing margin.