SPRAD21B march   2023  – may 2023 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 AM62x Family of Devices
      1. 1.1.1 AM625
      2. 1.1.2 AM623
    2. 1.2 AM62Ax Family of Devices
      1. 1.2.1 AM62A7
      2. 1.2.2 AM62A7-Q1
      3. 1.2.3 AM62A3
      4. 1.2.4 AM62A3-Q1
  5. 2 Related Collaterals
    1. 2.1 Hardware Design Guide
      1. 2.1.1 AM625/AM623
      2. 2.1.2 AM62A7 / AM62A3
  6. 3 Device Selection
    1. 3.1 Data Sheet
    2. 3.2 Peripheral Instance Naming Convention
    3. 3.3 Device Ordering and Quality
  7. 4 Power Architecture
    1. 4.1 Generating Supply Rails
      1. 4.1.1 AM625 / AM623
        1. 4.1.1.1 PMIC (Power Management IC)
          1. 4.1.1.1.1 Additional Reference
        2. 4.1.1.2 Discrete Power
          1. 4.1.1.2.1 DC/DC Converter
          2. 4.1.1.2.2 LDO
      2. 4.1.2 AM62A7 / AM62A3
        1. 4.1.2.1 PMIC (Power Management IC)
    2. 4.2 Power Management
      1. 4.2.1 Load Switch
  8. 5 General Recommendations
    1. 5.1 Processor Performance Evaluation Module (EVM)
    2. 5.2 EVMs Versus Data sheet
      1. 5.2.1 Notes About Component Selection
        1. 5.2.1.1 Series Termination
        2. 5.2.1.2 Parallel Termination
        3. 5.2.1.3 External ESD Protection
      2. 5.2.2 Additional Information
    3. 5.3 Before You Begin The design
      1. 5.3.1 Documentation
      2. 5.3.2 Processor Pinout Verification
        1. 5.3.2.1 Verification of Unused Processor Pins
      3. 5.3.3 Peripheral Instance Naming
      4. 5.3.4 Processor Related Queries and Clarifications
  9. 6 Processor (AM625 / AM623 and AM62A7 / AM62A3) Specific Recommendations
    1. 6.1 Common (Processor Start-Up) Connection
      1. 6.1.1 Power Supply
        1. 6.1.1.1 Supplies for Core and Peripherals
        2. 6.1.1.2 Supply for I/O Groups
        3. 6.1.1.3 Supply for eFuse ROM Programming (VPP)
        4. 6.1.1.4 Supply Connection When Partial I/O (Low Power Mode) Configuration is Used
        5. 6.1.1.5 Additional Information
      2. 6.1.2 Capacitors for Power Supply Rails
        1. 6.1.2.1 AM625/AM623
        2. 6.1.2.2 AM62A7 / AM62A3
        3. 6.1.2.3 Additional Information
      3. 6.1.3 Processor Clock
        1. 6.1.3.1 Clock Inputs
          1. 6.1.3.1.1 High Frequency Oscillator (MCU_OSC0_XI/ MCU_OSC0_XO)
          2. 6.1.3.1.2 Low Frequency Oscillator (WKUP_LFOSC0_XI/ WKUP_LFOSC0_XO)
          3. 6.1.3.1.3 EXT_REFCLK1 (External Clock Input to Main Domain)
        2. 6.1.3.2 Clock Outputs
      4. 6.1.4 Processor Reset
        1. 6.1.4.1 Reset Input
        2. 6.1.4.2 Reset Status Output
        3. 6.1.4.3 Additional Information
      5. 6.1.5 Configuration of Boot Modes
        1. 6.1.5.1 Boot Mode Isolation Buffers Use Case and Optimization
        2. 6.1.5.2 Bootmode Selection
          1. 6.1.5.2.1 Note About USB Boot Mode
        3. 6.1.5.3 Additional Information
    2. 6.2 JTAG and EMU for Debug
      1. 6.2.1 Additional Information
  10. 7 Processor Peripherals
    1. 7.1 Supply Connections for I/O Groups
    2. 7.2 Memory Interface (DDR4, LPDDR4, MMCSD (eMMC/SD/SDIO), OSPI/QSPI and GPMC)
      1. 7.2.1 DDR Subsystem (DDRSS)
        1. 7.2.1.1 DDR4
          1. 7.2.1.1.1 AM625/AM623
            1. 7.2.1.1.1.1 Configuration
            2. 7.2.1.1.1.2 Routing Topology and Terminations
            3. 7.2.1.1.1.3 Signals Termination and Calibration Resistors
            4. 7.2.1.1.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.1.1.5 Data Bit or Byte Swapping
          2. 7.2.1.1.2 AM62A7 / AM62A3
        2. 7.2.1.2 LPDDR4
          1. 7.2.1.2.1 AM625/AM623
            1. 7.2.1.2.1.1 Configuration
            2. 7.2.1.2.1.2 Routing Topology and Terminations
            3. 7.2.1.2.1.3 Signals Termination and Calibration Resistors
            4. 7.2.1.2.1.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.1.5 Data Bit or Byte Swapping
          2. 7.2.1.2.2 AM62A7 / AM62A3
            1. 7.2.1.2.2.1 Configuration
            2. 7.2.1.2.2.2 Routing Topology and Terminations
            3. 7.2.1.2.2.3 Signals Termination and Calibration Resistors
            4. 7.2.1.2.2.4 Capacitors for the Power Supply Rails
            5. 7.2.1.2.2.5 Data Bit or Byte Swapping
      2. 7.2.2 MMCSD (Multi-Media Card/Secure Digital)
        1. 7.2.2.1 MMC0 - Embedded Multi-Media Card (eMMC) Interface
          1. 7.2.2.1.1 I/O Power Supply
          2. 7.2.2.1.2 Reset
          3. 7.2.2.1.3 Signals Termination
          4. 7.2.2.1.4 Capacitors for the Power Supply Rails
          5. 7.2.2.1.5 Additional Information
        2. 7.2.2.2 MMC0 – Secure Digital (SD) Card Interface
        3. 7.2.2.3 MMC1 / MMC2 – Secure Digital (SD) Card Interface
          1. 7.2.2.3.1 I/O Power Supply
          2. 7.2.2.3.2 Reset
          3. 7.2.2.3.3 Signals Termination
          4. 7.2.2.3.4 Protection
          5. 7.2.2.3.5 Capacitors for the Power Supply Rails
        4. 7.2.2.4 Additional Information
      3. 7.2.3 Octal Serial Peripheral Interface (OSPI) and Quad Serial Peripheral Interface (QSPI)
        1. 7.2.3.1 I/O Power Supply
        2. 7.2.3.2 Reset
        3. 7.2.3.3 Signals Termination
        4. 7.2.3.4 Loopback Clock
        5. 7.2.3.5 Interface to Multiple Devices
        6. 7.2.3.6 Capacitors for the Power Supply Rails
      4. 7.2.4 General-Purpose Memory Controller (GPMC)
        1. 7.2.4.1 I/O Power Supply
        2. 7.2.4.2 GPMC Interface
        3. 7.2.4.3 Reset
        4. 7.2.4.4 Signals Termination
        5. 7.2.4.5 Capacitors for the Power Supply Rails
    3. 7.3 External Communication Interface (Ethernet, USB, PRUSS, UART and CAN)
      1. 7.3.1 Ethernet Interface Using Common Platform Ethernet Switch 3-Port Gigabit (CPSW3G)
        1. 7.3.1.1 I/O Power Supply
        2. 7.3.1.2 Reset
        3. 7.3.1.3 PHY Pin Strapping
        4. 7.3.1.4 Ethernet PHY (and MAC) Operation and MII Interface Clock
          1. 7.3.1.4.1 Crystal
          2. 7.3.1.4.2 Oscillator
          3. 7.3.1.4.3 Processor Clock Output (CLKOUT0)
        5. 7.3.1.5 Reduced Gigabit Media Independent Interface (RGMII) /Reduced Media Independent Interface (RMII) Signals Termination
        6. 7.3.1.6 MAC (Media Access Controller) to MAC Interface
        7. 7.3.1.7 Management Data Input/Output (MDIO) Interface
        8. 7.3.1.8 Ethernet Medium Dependent Interface (MDI) Interface Including Magnetics
        9. 7.3.1.9 Capacitors for the Power Supply Rails
      2. 7.3.2 Universal Serial Bus (USB)
        1. 7.3.2.1 USB Used
          1. 7.3.2.1.1 USB Host Interface
          2. 7.3.2.1.2 USB Device Interface
          3. 7.3.2.1.3 USB Dual-Role-Device Interface
        2. 7.3.2.2 USB Not Used
        3. 7.3.2.3 Additional Information
      3. 7.3.3 Programmable Real-Time Unit Subsystem (PRUSS)
        1. 7.3.3.1 AM625 / AM623
        2. 7.3.3.2 AM62A7 / AM62A3
      4. 7.3.4 Universal Asynchronous Receiver/Transmitter (UART)
      5. 7.3.5 Controller Area Network (CAN)
    4. 7.4 On-Board Synchronous Communication Interface (MCSPI, MCASP and I2C)
      1. 7.4.1 Multichannel Serial Peripheral Interface (MCSPI) and Multichannel Audio Serial Ports (MCASP)
      2. 7.4.2 Inter-Integrated Circuit (I2C)
    5. 7.5 User Interface (CSIRX0, DPI, OLDI), GPIO and Internal Diagnostics
      1. 7.5.1 Camera Serial Interface (CSI-Rx (CSI-2 port, CSIRX0 Instance))
        1. 7.5.1.1 CSIRX0 Used
        2. 7.5.1.2 CSIRX0 Not Used
      2. 7.5.2 Display Subsystem
        1. 7.5.2.1 DPI (Display Parallel) Interface
          1. 7.5.2.1.1 I/O Power Supply
          2. 7.5.2.1.2 Reset
          3. 7.5.2.1.3 Connection
          4. 7.5.2.1.4 Signals Termination
          5. 7.5.2.1.5 Capacitors for the Power Supply Rails
        2. 7.5.2.2 Open LVDS Display Interface (OLDI)
          1. 7.5.2.2.1 AM625 / AM623
            1. 7.5.2.2.1.1 OLDI Used
              1. 7.5.2.2.1.1.1 I/O Power Supply
              2. 7.5.2.2.1.1.2 Reset
              3. 7.5.2.2.1.1.3 OLDI Interface Compatibility
              4. 7.5.2.2.1.1.4 Capacitors for the Power Supply Rails
            2. 7.5.2.2.1.2 OLDI Not Used
            3. 7.5.2.2.1.3 Additional Information
          2. 7.5.2.2.2 AM62A7 / AM62A3
      3. 7.5.3 General Purpose Input/Output (GPIO)
        1. 7.5.3.1 CLKOUT Available on GPIO
        2. 7.5.3.2 Termination and Buffering
        3. 7.5.3.3 Unused GPIO
        4. 7.5.3.4 Additional Information
      4. 7.5.4 Internal Diagnostics
        1. 7.5.4.1 Monitoring of Voltage Using Processor
          1. 7.5.4.1.1 Voltage Monitor Pins Used
          2. 7.5.4.1.2 Voltage Monitor Pins Not Used
        2. 7.5.4.2 Temperature Monitoring
          1. 7.5.4.2.1 AM625 / AM623
          2. 7.5.4.2.2 AM62A7 / AM62A3
          3. 7.5.4.2.3 Additional Information
        3. 7.5.4.3 Termination of Error Signal Output MCU_ERRORn
        4. 7.5.4.4 Oscillator Clock Loss Detection
    6. 7.6 Verifying Board Level Design Issues
      1. 7.6.1 Pinmux
      2. 7.6.2 Terminations (Pullups)
      3. 7.6.3 General Debug
        1. 7.6.3.1 Clock Output for Board Bring-Up, Test or Debug
        2. 7.6.3.2 Additional Information
  11. 8 Notes For Layout (To be Added on the Schematic)
  12. 9 Design Simulation
  13. 10Additional References
  14. 11Summary
  15. 12References
    1. 12.1 AM625/AM623
    2. 12.2 AM62A7/AM62A3
    3. 12.3 Common
  16. 13Terminology
  17. 14Revision History
Application Note

AM625/AM623 and AM62A7/AM62A3 Schematic Design and Review Checklist