DAC3482

ACTIVO

Convertidor digital a analógico (DAC) de doble canal, 16 bits, 1,25 GSPS, 1x-16x de interpolación

Detalles del producto

Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel LVDS Sample/update rate (Msps) 1250 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (typ) (mW) 800 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel LVDS Sample/update rate (Msps) 1250 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (typ) (mW) 800 SFDR (dB) 82 Architecture Current Source Operating temperature range (°C) -40 to 85 Reference type Int
NFBGA (ZAY) 196 144 mm² 12 x 12 WQFN-MR (RKD) 88 81 mm² 9 x 9
  • Very low power: 900mW at 1.25GSPS, full operating conditions
  • Multi-DAC synchronization
  • Selectable 2x, 4x, 8x, 16x interpolation filter
    • Stop-band attenuation > 90dBc
  • Flexible on-chip complex mixing
    • Fine mixer with 32-bit NCO
    • Power saving coarse mixer: ± n×Fs/8
  • High performance, low jitter clock multiplying PLL
  • Digital I and Q correction
    • Gain, phase, offset, and group delay correction
  • Digital inverse sinc filter
  • Flexible LVDS input data bus
    • Word- or byte-wide interface
    • 8 Sample input FIFO
    • Data pattern checker
    • Parity check
  • Temperature sensor
  • Differential scalable output: 10mA to 30mA
  • Multiple package options: 88 Pin 9 x 9mm WQFN-MR and 196-ball 12mm x12mm
  • Very low power: 900mW at 1.25GSPS, full operating conditions
  • Multi-DAC synchronization
  • Selectable 2x, 4x, 8x, 16x interpolation filter
    • Stop-band attenuation > 90dBc
  • Flexible on-chip complex mixing
    • Fine mixer with 32-bit NCO
    • Power saving coarse mixer: ± n×Fs/8
  • High performance, low jitter clock multiplying PLL
  • Digital I and Q correction
    • Gain, phase, offset, and group delay correction
  • Digital inverse sinc filter
  • Flexible LVDS input data bus
    • Word- or byte-wide interface
    • 8 Sample input FIFO
    • Data pattern checker
    • Parity check
  • Temperature sensor
  • Differential scalable output: 10mA to 30mA
  • Multiple package options: 88 Pin 9 x 9mm WQFN-MR and 196-ball 12mm x12mm

The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS.

The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.

Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.

The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a small 88 pin 9 x 9mm WQFN-MR package or 196-ball 12 x12mm NFBGA package.

Low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.

The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25GSPS.

The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.

Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.

The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a small 88 pin 9 x 9mm WQFN-MR package or 196-ball 12 x12mm NFBGA package.

Low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Fecha
* Data sheet DAC3482, Dual-Channel, 16-Bit, 1.25GSPS Digital-to-Analog Converter (DAC) datasheet (Rev. G) PDF | HTML 18 ene 2024
Application note QFN and SON PCB Attachment (Rev. C) PDF | HTML 06 dic 2023
Application note Effects of Clock Spur on High Speed DAC Performance (Rev. A) 18 may 2015
Design guide TSW308x Wideband Digital to RF Transmit Solution Design Guide 03 sep 2013
Design guide Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) 14 ago 2013
Application note Using DAC348x with Fault Detection and Auto Output Shut-off Feature 21 feb 2013
Application note DAC348x Device Configuration and Synchronization 18 feb 2013
Application note Effects of Clock Noise on High Speed DAC Performance 08 nov 2012
Application note High Speed, Digital-to-Analog Converters Basics (Rev. A) 23 oct 2012
Application note Design Summary Multi-row Quad Flat No-lead (MRQFN) 29 ago 2012
User guide Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) 10 jul 2012
User guide TSW1400 Pattern Generators 03 may 2012
Application note Configuring and Optimizing On-Chip PLL of the DAC348x 26 ene 2012
User guide TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) 29 dic 2011

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

TSW3085EVM — Placa de evaluación de cadena de señal de transmisión de banda ancha y diseño de referencia

The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)

Guía del usuario: PDF
GUI para el módulo de evaluación (EVM)

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Productos y hardware compatibles

Productos y hardware compatibles

GUI para el módulo de evaluación (EVM)

SLAC483 DAC348x EVM Software GUI

Productos y hardware compatibles

Productos y hardware compatibles

GUI para el módulo de evaluación (EVM)

SLAC507 TSW308x EVM Software

Productos y hardware compatibles

Productos y hardware compatibles

GUI para el módulo de evaluación (EVM)

SLLC420 TSW3100EVM GUI v2.7

Productos y hardware compatibles

Productos y hardware compatibles

Modelo de simulación

DAC3482 IBIS Model (Rev. A)

SLAM073A.ZIP (33 KB) - IBIS Model
Modelo de simulación

TINA-TI SPICE Models: Analog Interfacing Networks for DAC348x and Modulators

SLUC481.ZIP (198 KB) - TINA-TI Spice Model
Esquema

TSW3100 Design Package

SLLC424.ZIP (15830 KB)
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® para TI es un entorno de diseño y simulación que ayuda a evaluar la funcionalidad de los circuitos analógicos. Esta completa suite de diseño y simulación utiliza un motor de análisis analógico de Cadence®. Disponible sin ningún costo, PSpice para TI incluye una de las bibliotecas de modelos (...)
Diseños de referencia

TIDA-00077 — Redes de interconexión analógica para DAC348x y moduladores

The analog interface circuits in this reference design are often used between current-source based digital-to analog converters (DAC) and quadrature modulators. While the DAC348x is used as an example of a TI high-speed DAC, the circuits can be applied to other current-source based converters with (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00076 — Mediciones de la relación de potencia del canal adyacente (ACPR) y la magnitud del vector de error (

This reference design discusses the use of the TSW3085EVM with the TSW3100 pattern generator to test adjacent channel power ratio (ACPR) and error vector magnitude (EVM) measurements of LTE baseband signals. By using the TSW3100 LTE GUI, patterns are loaded into the TSW3085EVM which is comprised of (...)
Guía del usuario: PDF
Esquema: PDF
Diseños de referencia

TIDA-00069 — Ejemplo de FPGA Firmware de cómo conectar FPGA Altera a convertidores de datos de interfaz LVDS de a

This reference design and the associated example Verilog code can be used as a starting point for interfacing Altera FPGAs to Texas Instruments' high-speed LVDS-interface analog-to-digital converters (ADC) and digital-to-analog converters (DAC). The firmware implementation is explained and the (...)
Guía del usuario: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
NFBGA (ZAY) 196 Ultra Librarian
WQFN-MR (RKD) 88 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL)/reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

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