ADS5546

ACTIVO

Convertidor analógico a digital (ADC) de 14 bits y 190 MSPS

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Hoja de datos

document-pdfAcrobat 14-Bits 190 MSPS ADC With DDR LVDS/CMOS Outputs datasheet (Rev. D) (Inglés)

ADS5546

ACTIVO

Haga su pedido ahora

Detalles del producto

Sample rate (max) (Msps)

190

Resolution (Bits)

14

Number of input channels

1

Interface type

Parallel CMOS, Parallel LVDS

Analog input BW (MHz)

500

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

1130

Architecture

Pipeline

SNR (dB)

73.8

ENOB (Bits)

11.8

SFDR (dB)

90

Operating temperature range (°C)

-40 to 85

Input buffer

No

Sample rate (max) (Msps)

190

Resolution (Bits)

14

Number of input channels

1

Interface type

Parallel CMOS, Parallel LVDS

Analog input BW (MHz)

500

Features

High Performance

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

1130

Architecture

Pipeline

SNR (dB)

73.8

ENOB (Bits)

11.8

SFDR (dB)

90

Operating temperature range (°C)

-40 to 85

Input buffer

No

VQFN (RGZ)

48

49 mm² (7 mm × 7 mm)

Maximum Sample Rate: 190 MSPS
14-Bit Resolution
No Missing Codes
Total Power Dissipation 1.1 W
Internal Sample and Hold
73.2-dBFS SNR at 70-MHz IF
87-dBc SFDR at 70-MHz IF, 0 dB gain
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
Reduced Power Modes at Lower Sample Rates
Supports input clock amplitude down to 400 mV_PP
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
Programmable Output Clock position to ease data capture
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

Maximum Sample Rate: 190 MSPS
14-Bit Resolution
No Missing Codes
Total Power Dissipation 1.1 W
Internal Sample and Hold
73.2-dBFS SNR at 70-MHz IF
87-dBc SFDR at 70-MHz IF, 0 dB gain
Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
Reduced Power Modes at Lower Sample Rates
Supports input clock amplitude down to 400 mV_PP
Clock Duty Cycle Stabilizer
No External Reference Decoupling Required
Internal and External Reference Support
Programmable Output Clock position to ease data capture
3.3-V Analog and Digital Supply
48-QFN Package (7 mm × 7 mm)
APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems

ADS5546 is a high performance 14-bit, 190-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.

In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. ADS5546 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.

The device is specified over the industrial temperature range (-40°C to 85°C).

ADS5546 is a high performance 14-bit, 190-MSPS A/D converter. It offers state-of-the art functionality and performance using advanced techniques to minimize board space. Using an internal sample and hold and low jitter clock buffer, the ADC supports both high SNR and high SFDR at high input frequencies. It features programmable gain options that can be used to improve SFDR performance at lower full-scale analog input ranges.

In a compact 48-pin QFN, the device offers fully differential LVDS DDR (Double Data Rate) interface while parallel CMOS outputs can also be selected. Flexible output clock position programmability is available to ease capture and trade-off setup for hold times. At lower sampling rates, the ADC can be operated at scaled down power with no loss in performance. ADS5546 includes an internal reference, while eliminating the traditional reference pins and associated external decoupling. The device also supports an external reference mode.

The device is specified over the industrial temperature range (-40°C to 85°C).

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Documentación técnica

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Ver todo 9

Documentación principal	Tipo	Título
*	Hoja de datos	14-Bits 190 MSPS ADC With DDR LVDS/CMOS Outputs datasheet (Rev. D)	7/05/2007
	Nota sobre la aplicación	Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)	22/05/2015
	Nota sobre la aplicación	Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)	19/07/2013
	Nota sobre la aplicación	Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)	10/09/2010
	Nota sobre la aplicación	Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio	28/04/2009
	Nota sobre la aplicación	CDCE62005 as Clock Solution for High-Speed ADCs	4/09/2008
	Nota sobre la aplicación	CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters	8/06/2008
	Nota sobre la aplicación	Phase Noise Performance and Jitter Cleaning Ability of CDCE72010	2/06/2008
	Nota sobre la aplicación	QFN Layout Guidelines	28/07/2006

Diseño y desarrollo

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