DAC5681Z

ACTIVO

Convertidor digital a analógico (DAC) de 16 bits, 1,0 GSPS, con interpolación 1x-4x

Detalles del producto

Resolution (Bits) 16 Number of DAC channels 1 Interface type Parallel LVDS Sample/update rate (Msps) 1000 Features Ultra High Speed Rating Catalog Interpolation 1x, 2x, 4x Power consumption (typ) (mW) 800 SFDR (dB) 81 Architecture Current Sink Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels 1 Interface type Parallel LVDS Sample/update rate (Msps) 1000 Features Ultra High Speed Rating Catalog Interpolation 1x, 2x, 4x Power consumption (typ) (mW) 800 SFDR (dB) 81 Architecture Current Sink Operating temperature range (°C) -40 to 85 Reference type Int
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • 16-Bit Digital-to-Analog Converter (DAC)
  • 1.0 GSPS Update Rate
  • 16-Bit Wideband Input LVDS Data Bus
    • 8 Sample Input FIFO
  • High Performance
    • 73-dBc ACLR WCDMA TM1 at 180 MHz
  • 2x to 32x Clock Multiplying PLL/VCO
  • 2x or 4x Interpolation Filters
    • Stopband Transition 0.4–0.6 Fdata
    • Filters Configurable in Either Low-Pass or
      High-Pass Mode
      • Allows Selection of Higher Order Image
  • On-Chip 1.2-V Reference
  • 2 to 20-mA Differential Scalable Output
  • 64-Pin 9-mm × 9-mm VQFN Package
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

All other trademarks are the property of their respective owners

  • 16-Bit Digital-to-Analog Converter (DAC)
  • 1.0 GSPS Update Rate
  • 16-Bit Wideband Input LVDS Data Bus
    • 8 Sample Input FIFO
  • High Performance
    • 73-dBc ACLR WCDMA TM1 at 180 MHz
  • 2x to 32x Clock Multiplying PLL/VCO
  • 2x or 4x Interpolation Filters
    • Stopband Transition 0.4–0.6 Fdata
    • Filters Configurable in Either Low-Pass or
      High-Pass Mode
      • Allows Selection of Higher Order Image
  • On-Chip 1.2-V Reference
  • 2 to 20-mA Differential Scalable Output
  • 64-Pin 9-mm × 9-mm VQFN Package
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

All other trademarks are the property of their respective owners

The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x to 4x interpolation filters, on-board clock multiplier, and internal voltage reference. The DAC5681Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5681Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by on-board 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.

The DAC5681Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin VQFN package. Other members of the family include the dual-channel, interpolating DAC5682Z and the single-channel, non-interpolating DAC5681.

The DAC5681Z is a 16-bit 1.0 GSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x to 4x interpolation filters, on-board clock multiplier, and internal voltage reference. The DAC5681Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5681Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by on-board 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.

The DAC5681Z is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin VQFN package. Other members of the family include the dual-channel, interpolating DAC5682Z and the single-channel, non-interpolating DAC5681.

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos 16-BIT, 1.0 GSPS 2x-4x INTERPOLATING DAC. datasheet (Rev. G) 3/12/2015
Nota sobre la aplicación High Speed, Digital-to-Analog Converters Basics (Rev. A) 23/10/2012
Guía del usuario TSW1400 Pattern Generators 3/05/2012
Nota sobre la aplicación Passive Terminations for Current Output DACs 10/11/2008
Nota sobre la aplicación CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 8/06/2008
Nota sobre la aplicación Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 2/06/2008

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

DAC5681ZEVM — Módulo de evaluación de DAC5681Z para convertidor digital a analógico, 16 bits, 1,0 GSPS, 1x-4x con

The DAC5681ZEVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' single-channel 16-bit 1.0 GSPS digital-to-analog converter (DAC) featuring a fll 1GSPS DDR LVDS interface, integrated 2x/4x interpolation filters, on-board clock multiplier and internal (...)

Guía del usuario: PDF
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Placa de evaluación

ABACO-3P-FMC204FPGA — Tarjeta intermedia FPGA Abaco Systems® FMC204

The FMC204 is a quad channel D/A FMC daughter card. The card is based on TI's DAC5681Z dual channel 16-bit 1 Gsps device. The FMC204 daughter card is mechanically and electrically compliant to FMC standard (ANSI/VITA 57.1). The FMC204 has a high-pin count connector, front panel I/O, and can be (...)
Desde: Abaco Systems
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Tarjeta secundaria

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The FMC110 is a dual channel A/D and dual channel D/A FMC daughter card. The card is based on TI's ADS5400 dual channel 12-bit 1 Gsps ADC and TI's DAC5681Z dual channel 16-bit 1 Gsps device. The FMC150 daughter card is mechanically and electrically compliant to FMC standard (ANSI/VITA 57.1). The (...)
Desde: Abaco Systems
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GUI para el módulo de evaluación (EVM)

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Esta interfaz gráfica de usuario (GUI) de convertidor de datos de alta velocidad pro es un programa para PC (compatible con Windows® XP/7/10) que está diseñado para ayudar en la evaluación de la mayoría de los convertidores de datos de alta velocidad (convertidor de señal analógica a digital [ADC] (...)

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GUI para el módulo de evaluación (EVM)

SLAC497 — DAC5682z EVM Software

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GUI para el módulo de evaluación (EVM)

SLLC420 — TSW3100EVM GUI v2.7

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Modelo de simulación

DAC5681, DAC5681Z, DAC5682Z IBIS Model (Rev. A)

SLLC320 (38 KB) - Modelo IBIS
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Herramienta de cálculo

SLAC169 — DAC5682 LPF Calculator

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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
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Pedidos y calidad

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

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