TSW3084EVM

Wideband Transmit Signal Chain Evaluation Board and Reference Design

TSW3084EVM

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Overview

The TSW3084EVM Evaluation Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit solution the TSW3084EVM includes the LMK04806B for clocking the DAC3484 digital-to-analog converter (DAC), as well as two TRF3705 for up-converting the I/Q outputs from the 4-channel DAC to RF carriers.

The DAC3484 is a four-channel, ultra-low power 16-bit 1.25 GSPS DAC with an efficient multiplexed 16-bit wide bus capable of 312MSPS per DAC input rates.

The TRF3705 is a high performance complex RF modulator with a 300 MHz to 4 GHz output range.

The LMK04806B is a low noise clock generator and jitter cleaner capable of jitter below 150fs rms and output frequencies up to 1300MHz.

The EVM can be used along with the TSW3100/TSW1400 pattern generator to perform a wide range of test procedures to the LVDS port up to a maximum rate of 1.25 GSPS. The TSW1406 can be used for low cost, simple patterns up to 1 GSPS. Besides providing a high-quality, low jitter DAC sampling clock to the DAC3484, the LMK04806B also provides FPGA clocks to the TSW1400/TSW1406/TSW3100 as an FPGA reference clock. The transmit RF signal path also includes an amplifier and programmable attenuator.

Features
  • Includes LMK04806B for clock generation and jitter cleaning
  • Direct connection to TSW3100/TSW1400/TSW1406 signal generator
  • Comprehensive test capability for the transmitter (DAC3484 quad DAC and two TRF3705 IQ Modulators) at analog baseband, IF and RF outputs
  • Software support with a full featured GUI for easy testing and prototyping
  • FMC-DAC-Adapter card compatible to connect with FMC interconnect headers available Xilinx FPGA EVMs
  • Direct compatibility with HSMC headers on Altera FPGA EVMs
  • Clock jitter cleaners & synchronizers
    LMK04803 Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 1.9 GHz VCO LMK04805 Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.2 GHz VCO LMK04806 Low Noise Clock Jitter Cleaner With Dual Cascaded PLLs and Integrated 2.5 GHz VCO LMK04808 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs and Integrated 2.9 GHz VCO

     

    High-speed DACs (>10MSPS)
    DAC3484 Quad-Channel, 16-Bit, 1.25-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)

     

    IQ modulators
    TRF3705 300MHz to 4GHz Quadrature Modulator

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    Evaluation board

    TSW3084EVM – Complete RF SIgnal Chain Evaluation Module

    GUI for evaluation module (EVM)

    TSW308x EVM Software (Rev. B) – SLAC507B.ZIP (123888KB)

    TI's Standard Terms and Conditions for Evaluation Items apply.

    Design files

    Technical documentation

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    Type Title Date
    More literature TSW3084EVM EU Declaration of Conformity (DoC) Jan. 02, 2019
    User guide TSW308x Evaluation Module (Rev. B) May 18, 2016
    User guide Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) Aug. 14, 2013
    User guide TSW3085EVM ACPR and EVM Measurements (TIDA-00076 Reference Guide) Dec. 29, 2011

    Related design resources

    Hardware development

    EVALUATION BOARD
    TSW1400EVMData Capture/Pattern Generator: Data Converter Evaluation Module With 8 LVDS Lanes up to 1.5Gbps
    TSW1406EVMData Capture/Pattern Generator: Data Converter Evaluation Module With 8 LVDS Lanes up to 1.0Gbps

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