The two primary circuits, required to maximize the performance of a high-precision, successive approximation register (SAR) ADCs, are the input driver and the reference driver circuits. For details on selecting the amplifier, refer to the ADS8354 datasheet, Section 9.1.

The THS4531A has been minded to work in combination with the ADS8354. Indeed, the common mode or DC-level of the input signal (2.5 V nominal) is provided to the THS4531A directly from the reference output of the ADS8354 itself to minimize potential offset and drift errors.

The differential input full scale range of the ADS8354 was configured to ±2 × V_REF. With the reference voltage of V_REF = 2.5 V, this yields a FSR of ±5 V. The maximum Sin/Cos encoder’s differential input voltage is 1.2 V_PP. A voltage of higher than 1.35 V_PP should still be detected as failure. A safety margin of 50% is added to the maximum peak-to-peak voltage, which is then 1.8 V_PP. To match the ADC full-scale input range, the gain of the THS4531A should be 5.5. However, to remain in the linear output voltage range of the THS4531A at a 5-V supply, which is at least 0.25 to 4.8 V, the gain should be reduced by around 10%, hence the ideal differential amplifier gain would be 5.

To ensure the minimum gain error and especially drift between the channels, high-precision, matched resistors with 0.1% accuracy and 2-ppm/K temperature drift are required. To minimize noise, the feedback resistors should be chosen in the lower kΩ range (see Section 1.4).

A precision matching resistor divider is used to keep potential gain errors as small as possible. Refer to the MPMT10015001AT1 datasheet for details.

Due to the gain of 5, a typical 1-V_PP input signal leverages around 50% of the ADC full-scale range (FSR), which results in a loss of 1-bit of precision, therefore yielding an equivalent 15-bit resolution. The lower input voltage of 0.6 V_PP will leverage around 25% of the FSR, which equals typically 14-bit resolution.

Figure 4-5 shows the schematics of the high-precision analog signal path; the matched gain setting resistors are R18, R27, R30, and R37.

The series 10-Ω resistors R21, R25 and the 2.2-nF capacitor C29 (R33, R36, and C39 for ADS8354 channel B) from the anti-aliasing filter. The filter capacitor C29 (C39), connected across the ADC inputs, filters the noise from the front end drive circuitry, reduces the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor should be at least 10 times the specified value of the ADC sampling capacitance. For these devices, the input sampling capacitance is equal to 40 pF. The capacitor should be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time. To avoid amplifier stability issues, 10-Ω series isolation resistors R21, R25 (R31, R39) are used at the output of the amplifiers. For details, refer to the Section 9.1 of the ADS8354 datasheet.

To minimize the impact of an offset drift of the ADC reference REFIO_A and REFIO_B, the ADC references are used to bias the common mode output voltage of the THS4531A. To buffer and decouple the V_OCM signal at the THS4531A, small RC filters R24/C32 and R35/C42 R28, R29, C36, and C37 are added close to each pin.

The ADS8354 reference voltages REFIO_A and REFIO_B are decoupled with a 10-uF capacitor C36 and C37, respectively and a 0.22-Ω resistor is added in series to avoid high-frequency oscillations.

To optimize the layout for cross-talk with minimum use of via for the critical signals A+, A– and B+, B–, the following connections have been made.

1. The differential input signal A (A+, A–) has been inverted at the input of the THS4531A and fed into the ADS8354 input channel B.
2. The differential output signal of the THS4531A, B+ and B– have been connected inverted to the ADS8354 input pins AINP_A to B– and AINM_A to B+

This results in the following hardware relationship: The ADS8354 channel B equals the inverted Sin/Cos encoder signal A; the ADS8354 channel A equals the inverted Sin/Cos encoder signal B.

Figure 4-5 Sin and Cos Signal Chain With Dual THS4531A and ADS8354

To achieve a higher noise immunity with reduced bandwidth, a capacitor of 10 pF (1% or better) or higher, pending desired bandwidth is recommend in the feedback path in parallel to the 5 kΩ. See Section 4.5.

The configuration of the ADS8354 registers through serial interface is explained in Section 4.3.