TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

7.3.1.2 One Mechanical Revolution Test at Maximum Speed

For this test, the high-resolution interpolated angle over one mechanical revolution was calculated within TIDA-00176 connected to the Piccolo F28069M LaunchPad. The sample rate was set to 32 kHz at
80-MHz CPU clock.

The aim of the test is to verify the interpolation algorithm works at maximum input signal frequency of
500 kHz, without missing any incremental count or mismatching the interpolated phase (arc tangent) and the corresponding line count (QEP) for example, due to mismatch of latching the analog samples and the QEP counter. This would translate into a larger error then the quantization noise measured in Section 7.3.1.1.

For that purpose, a 360-degree spin of the encoder has been emulated using the dual signal generator. The test is performed with the dual output signal generator in the following way: The two output signals are coupled in amplitude and frequency, with a 90-degrees phase shift. The two signals are then applied as input at the TIDA-00176 encoder connector J9 A+/A– and B+/B– pins.

The total interpolated angle was stored in the F28069M RAM and read through CCS memory dump.

The calculated high-resolution angle is compared with an ideal phase assuming an encoder with 2000 line counts. Therefore, 2000 signal periods at 500K kHz equal one emulated revolution. The total angular phase ramps at a rate of 360 degrees × 500 kHz/2000 = 90,000deg/s. Table 7-6 provides the timings for
1 µs and for 100 ns, which equals one F28069M CPU clock at 80 MHz.

Table 7-6 Angular Speed for Sin/Cos Encoder With Line Count 2000 Running at 15000 rpm
IDEAL ANGULAR SPEEDANGLE CHANGE IN 1 µsANGLE CHANGE IN 12.5 (CPU CLOCK)
90,000 deg/s0.090.0011

A jitter on the signal generator as well as on the processor clock or even a CPU clock jitter of the host processor sampling the analog signal through SPI /CS cannot be avoided. Assuming an ideal ramp (due to a lack of reference) the measured angle will have a corresponding phase lag or lead, which translates into a velocity-dependent angle error.

Figure 7-29 shows the interpolated angle error assuming an ideal ramp (500 kHz, 2000 signal periods per revolution) measured at 32 khz, which yields 128 consecutive samples per revolution.

TIDA-00176 Error of Interpolated Angle Over One Revolution With Encoder Emulation (1 VPP, 500-kHz Input @ 32-kHz Sampling)Figure 7-29 Error of Interpolated Angle Over One Revolution With Encoder Emulation (1 VPP, 500-kHz Input @ 32-kHz Sampling)

As previously mentioned, the aim was not to test for accuracy, but to verify that no increment was lost. With a 2000-line count emulation, one incremental line count would correspond 360/2000 = 0.18 degrees. The angle error (difference) to an ideal straight line remains within ±0.001 degree; therefore, interpolation still works well at 500 kHz and no increment is lost.

As can be seen in figure the error is within ±0.0015 degrees. This is due to the CPU clock jitter as well as other jitter like from the signal generator source with the CPU clock jitter determining the minimum accuracy.

The reason for this distribution is due to jitter with the F28069 software to trigger the SPI transfer /CS of one or two CPU clock cycles. Falling edge of /CS latches the analog input. Just a jitter of 12.5 ns translates into a phase difference of around 12.5 ns/2000 ns × 360/2000 degrees ~ 0.0011 degrees. Therefore, the angle difference is actually a speed depended angle error (velocity) lag.