TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

1.1 Design Overview

This TI design implements an industrial temperature, EMC-compliant interface to Sin/Cos incremental position encoders with 1-VPP differential analog output signals, frequencies up to 500 kHz, and a 5-V supply voltage. The major building blocks of this TI design are the dual path analog signal chain, the high-speed comparator block, the power management block, and the interfaces to the Sin/Cos encoder as well as the interface to a host microcontroller for digital signal processing and high-resolution position calculation. A simplified system block diagram is shown in Figure 1-1, with the TI hardware design represented by the box in light green.

To allow for an easy evaluation of this design guide, an example firmware is provided for the TMS320F28069M InstaSPIN™-MOTION LaunchPad. The TMS320F28069M calculates the high-resolution angle position for both analog signal paths. One path is leveraging the external 16-bit dual ADC through SPI. The other path is using the F28069M embedded dual S/H 12-bit ADC. The angle is calculated with up to 28-bit resolution and output for evaluation through USB virtual COM port.

TIDA-00176 Simplified System Block Diagram of TIDA-00176 With Piccolo F28069M LaunchPadFigure 1-1 Simplified System Block Diagram of TIDA-00176 With Piccolo F28069M LaunchPad

The analog signal chain provides 120-Ω termination with EMC protection. The differential 1 VPP sine and cosine input signals are amplified and level-shifted, respectively. A dual signal path option is provided with an onboard high-speed, high-resolution dual 16-bit simultaneous sampling ADC with SPI and dual analog single-ended outputs with a 1.65-V bias voltage to interface to a microcontroller with embedded dual S/H ADC like the C2000™ Piccolo Real-time MCU family.

The comparator block features high-speed, low propagation delay and adjustable hysteresis for better noise immunity and converts the analog signals A, B, and the marker R into digital signals with a 3.3-V TTL-level to interface to a quadrature encoder pulse module like the QEP module on the C2000 Piccolo MCU.

The onboard wide-input range 24-V power supply provides the necessary voltages for analog signal chain as well as the 5.25-V supply voltage for the Sin/Cos encoder.

The Sin/Cos encoder can be either connected to a 15-pin shielded Sub-D connector or an 8-pin header. The interface to the host processor provides the analog single-ended signals A and B scaled from 0 to 3.3 V with a 1.65-V bias voltage, the digital signals for SPI and A, B, and R with a 3.3-V I/O. The digital output signals A, B, and R are often referred to as ABZ signals.

The design is tested for IEC61000-4-2, 4-4, and 4-5 (ESD, EFT, and Surge) as specified in the IEC 61800-3 standard for EMC immunity requirements and specific test methods applicable in adjustable speed, electrical-power drive systems.