TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

1.3.1.6 Resolution, Accuracy, and Speed Considerations

The ideal interpolated angle resolution is a function of the Sin/Cos encoder’s line count and the resolution of the dual ADC. The equivalent interpolated angle resolution can be calculated as:

Equation 6. TIDA-00176

Figure 1-7 illustrates the achievable interpolated angle resolution as a function of the line count for no interpolation, interpolation with an ideal 12-bit, and a 16-bit dual ADC.

TIDA-00176 Ideal Interpolated Angle Resolution versus Line Count versus ADC ResolutionFigure 1-7 Ideal Interpolated Angle Resolution versus Line Count versus ADC Resolution

The ideal resolution with a Sin/Cos encoder with 2048 line counts using a 16-bit dual ADC equals 28-bit, if the ADC’s full-scale input range is used.

This high resolution is typically not required for position control, but for very precise speed control, especially at lower mechanical speed. Figure 1-8 outlines the ideal speed resolution derived at a sample rate of 1.6 kHz without low-pass filtering. This assumes the industrial drive’s speed closed-loop control runs 10 times lower than the current closed-loop control and PWM at 16 kHz.

TIDA-00176 Ideal Speed Resolution versus Mechanical Speed at 1.6-kHz Sample Rate and Encoder With 1000 Line CountFigure 1-8 Ideal Speed Resolution versus Mechanical Speed at 1.6-kHz Sample Rate and Encoder With 1000 Line Count

Practically, low-pass filtering will be applied and improves resolution and immunity to noise, but with a filter specific propagation (group) delay or latency.

Following the ideal resolution, Table 1-7, Figure 1-9, and Figure 1-10 outline the impact of a quantization, offset, gain, or phase error to the interpolated angle.

Table 1-7 Phase Error Examples Analysis
ERROR SOURCEEXAMPLEPHASE ERROR [MAX]
Quantization of signals A and B12-bit0.012% [0.045°]
Offset error of signals A and B0.1%0.05% [0.18°]
Gain error of signals A and B0.1%0.04% [0.15°]
Phase shift between input signals A and B90 + 0.36° [0.1%]0.1% [0.36°]
TIDA-00176 Phase Error With +0.1% Offset With Signals A and BFigure 1-9 Phase Error With +0.1% Offset With Signals A and B
TIDA-00176 Phase Error With (90 + 0.36°) Phase Shift Between Signals A and BFigure 1-10 Phase Error With (90 + 0.36°) Phase Shift Between Signals A and B

Note that the phase error introduced due to a phase shift between the input signals A and B exhibits the double period. This signature can be leveraged for detection and correction of a constant phase shift using signal processing algorithms. However, these are beyond the scope of this design guide.