TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC

The parallel analog signal path should not impact the high-resolution path and especially the differential amplifier. Therefore, the differential signals A+, A–, B+, and B– are tapped off after the input termination and protection and are buffered using unity gain amplifiers with very low offset and especially offset drift. The following amplifier should convert the differential signals into a single-ended signal. The minimum bandwidth should be least 500 kHz, ideally higher to support incremental encoders with higher than
500-kHz output signals. The phase delay for the path to the comparator should be similar than the high-resolution path to ensure minimum analog signal phase shift.

The supply voltage should be a single supply 5 V.

To match the high-resolution channel, the sum of the offset drift of both op-amps should be at least 12-bit equivalent accuracy, ideally match the analog performance of the high-resolution channel. For the input buffer and the differential to single-ended conversion, the OPA2365 has been selected due to:

  • 2.2-V TO 5.5-V operation to leverage 5-V rail
  • Rail-to-rail I/O
  • Very low offset and offset drift: 200 µV (max) and 1 µV/K (typically)
  • Low voltage and current noise: 4.5 nV/SQRT(Hz) and 0.004 pA/SQRT(Hz)
  • Excellent THD+N: 0.0004%
  • High common mode rejection, CMRR: 100 dB (min)
  • Slew rate: 25 V/μs
  • Fast settling: 300 ns to 0.01% to drive external ADC

Another option is the OPA2322, which is a lower cost alternative, with 2-mV offset voltage and slightly reduced AC and DC performance.

The analog output voltage should be scaled from 0 to 3.3 V with a 1.65-V common mode. Applying the same criteria in Section 4.1.1 with a maximum 1.8-VPP input voltage, and a 10% margin with regards to the 3.3-V FSR, the gain yields 1.66.

Figure 4-6 shows the analog signal chain for channel A. The channel B is identical.

TIDA-00176 Analog Signal Path With Differential Input to Single-Ended Output for Signal A (sin), Signal B (cos) Not ShownFigure 4-6 Analog Signal Path With Differential Input to Single-Ended Output for Signal A (sin), Signal B (cos) Not Shown

The differential signals A_P and A_N are connected through a 220-Ω resistor to the non-inverting input of the OPA2365 (U8A and U8B). The OPA2365 (U8A and U8B) are configured as unity-gain buffer to avoid loading the source and introducing distortions. The 220-Ω series resistor limits the current into the non-inverting input of the OPA2365 in case of an over- or undervoltage event. The output of each buffer employs a small, adjustable RC-filter with, for example, R46 and C53 in above picture with f-3dB ~ 5 MHz for high-frequency noise reduction.

The following OPA2365 (U10A) is configured as differential to single-ended amplifier and level shifter. The gain is set to 1.66 and the output common mode voltage to 1.65 V through a low-drift voltage reference REF2033. An adjustable 5.6-pF feedback capacitor is added in parallel to the feedback resistor for HF noise filtering (f-3dB ~ 3.5 MHz), ideally matched to the THS4531A bandwidth. See Section 4.5.

Since the OPA2365 is supplied with 5 V, the output of the amplifier is clamped to 3.3 V (D17) with a series 10-Ω current limiting resistor (R48). This is to protect the following comparator (TLV3202/1) and an external ADC, which typically are 3.3-V I/O.

An anti-aliasing and decoupling RC network (R41/C48) is added to drive an external ADC. The filter was optimized for use with the embedded 12-bit dual S/H ADC in the C2000 Piccolo MCU family. For other ADCs, the filter has to be adjusted accordingly.

The 1.65-V bias voltage is decoupled with a 100-n capacitor (C57). Furthermore, LP RC filters have been added to reduce more and more HF noise components, in particular the one potentially coming from the switcher TPS54040A.