TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

4.1.3.1 Non-Inverting Comparator With Hysteresis

The input signals to all comparators are derived from the output of the single-ended to differential amplifier. The output signal is clamped to 3.3 V, as described earlier, and decoupled with a RC network (like R49, C54 in figure 19 for signal A) to avoid cross-talk to the analog single-ended signals A and B respectively.

The match the phase between the high-resolution path and this path, the RC decoupling network at the input to the comparator matches the RC filter (2×10 Ω and 2.2 nF) at the THS4531A output.

The TLV370x is configured as non-inverting comparator to detect the zero-crossing of the analog sin and cosine signals A and B as well as the index pulse R. Figure 4-7 shows the corresponding schematics for the signal A.

The switching threshold is set by the reference voltage VREF = 1.65 V (REF2033), which is also used to bias the single-ended analog signals for the differential to single-ended amplifiers. For each comparator, the reference input is taken from the REF2033 and decoupled with a 10-Ω series resistor and a 100-n capacitor.

A hysteresis is added for better noise immunity. The hysteresis (VTH+ – VTH–) of a non-inverting comparator can be calculated per Equation 7:

Equation 7. TIDA-00176

with VOut_High the high-level and VOut_Low the low level comparator output voltage, RF the feedback and RG the input resistor into the non-inverting comparator input.

For the configuration of this design as outlined in Figure 4-7, the hysteresis has been set to around 160 mV per Equation 8. Since R49 and R48 are magnitudes lower than R50, they can be neglected.

Equation 8. TIDA-00176

The upper and lower switching thresholds VTH+ and VTH– are defined per Equation 9 and Equation 10 with the reference voltage VREF = 1.65 V.

Equation 9. TIDA-00176
Equation 10. TIDA-00176
CAUTION:

The lower threshold is a function of the supply voltage. However, the supply voltage tolerance of this design 5%, as typical with most designs. A ±5% tolerance with the 3.3-V supply voltage would affect the lower threshold by only by ±16 mV, resulting VTH– range from approximately 1.56 to 1.59-V, hence still acceptable.

TIDA-00176 Signal A Comparator With HysteresisFigure 4-7 Signal A Comparator With Hysteresis

The 3.3-V supply of each comparator is decoupled with a 1-Ω series resistors and 100-nF capacitor to minimize cross-talk through the 3.3-V rail to other comparators. The RC low pass comprised of R49 and C54 is added to decouple the comparators switching node from the analog signal A/sin, which will be connected to an external ADC.

The hysteresis allows for a clean digital signal, which means it avoids fast switching due to noise around the zero crossing point. The hysteresis however introduces an additional propagation delay, which is depending on the analog signal amplitude VIN_PEAK-PEAK at the comparator input.

Equation 11. TIDA-00176

Assuming minimum input voltage of 0.3 VPP: The output of the differential- to single-ended amplifier (gain = 1.66) will have an amplitude of 0.5 VPP (0 to 100 kHz) and around 0.32 VPP at 500 kHz due to low-pass filter attenuation. The hysteresis corresponding phase delay of the digital signals A, B, and R will be around 30 degrees for a 0.32 VPP input at the comparator. At 500 kHz, this would translate into a total propagation delay of the comparator of around 170 ns + 40 ns = 210 ns.

Due to the low propagation delay of the TLV3201 with 40 ns only, the overall delay of the comparator block remains below 45 degrees up to 500 kHz.

The comparators for the signals B and R have the same settings. Also the buffering and gain stage for the index marker R is identical to the signals A and B. This is to ensure the phase of the index marker R is exactly in sync with the signal A and B up to a 500-kHz signal frequency. This ensures the zero Index Marker R will occur as specified, slightly before the rising edge of signals A and B. The index marker R defines the absolute zero position, and hence exact relation to signals A and B is required to avoid any position offset.