TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

4.1.1.1 Component Selection

A high-precision dual channel ADC is required to fulfill the design requirements. The ADS8354 has been selected for the following reasons:

  • High resolution (16-bit) with high precision (superb THD and SNR performance of –93 dB SNR,
    –100 dB THD)
  • Drop-in pin-compatible 14-bit and 12-bit versions for flexibility pending required resolution versus cost optimization
  • High speed (700 kSPS) and bandwidth to support at least 500-kHz analog input signals
  • Dual channel with true differential inputs and dual/independent reference voltages to improve immunity against common mode noise
  • Dual channel, simultaneous sampling of two channels to ensure zero phase shift between the sin and cos input signals A and B
  • Sample point triggered by hardware (falling edge of /CS) allows host processor to precise synchronize the sample point with the incremental counter latch.
  • Sample-and-hold circuit returns to sample mode after completing the conversion process, hence relative long sample times to settle to 16-bit accuracy
  • Dual, programmable, and buffered 2.5-V internal reference to provide common mode bias voltage to amplifier to almost cancel offset and offset drift related errors.
  • Serial interface to host processor (dual data) with up to 24-MHz clock frequency to minimize latency
  • Fully-specified over the extended industrial temperature range: –40°C to 125°C
  • Small package

TIDA-00176 ADS8354 Block DiagramFigure 4-2 ADS8354 Block Diagram

To leverage the ADS8354 performance, a fully differential high-speed amplifier with configurable output common mode voltage, like the THS45xx family, is required.

TIDA-00176 Differential Input to Differential Output AmplifierFigure 4-3 Differential Input to Differential Output Amplifier

The signal remains fully differential, the gain and optional filtering is defined by the input and feedback resistors and capacitors. The gain is set by the ration of RF/RG and the output common mode voltage is set by the input signal VOCM.

The THS4531A was chosen as it meets the topology, can drive the ADS8354, and meets the AC and DC requirements specified in Section 1.4. A single amplifier topology per package was used instead of the dual differential amplifier per package like the THS4532 for flexibility and easier PCB routing.

The key parameters of the THS4531A for use in this design are:

  • Fully differential architecture with adjustable output common mode voltage
  • High gain bandwidth: 27 MHz (6 MHz at G = 5)
  • Low distortions, THD –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
  • Low input voltage noise: 10 nV/√Hz (f = 1 kHz)
  • Very low offset, VOS: ±100 μV
  • Very low offset drift, VOS Drift: ±2 μV/°C (Industrial temperature range)
  • Single 5-V supply to leverage same supply than the ADS8354
  • Rail-to-rail output (RRO) and negative rail input (NRI) to maximize input and output signal swing