TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path

For the following tests, the entire high-resolution signal chain, featuring the differential amplifier THS4531A connected through an RC filter to the dual 16-bit ADC ADS8354 has been tested. A sinusoidal test signal has been injected at the encoder differential input pins and the 16-bit digital data has been analyzed.

The analysis has been done in the frequency domain to evaluate the performance on signal-to-noise ratio (SNR), total harmonic distortions (THD), signal-to-noise and distortion (SINAD), and effective number of bits (ENOB). Essentially, all these parameters are different ways of quantifying the noise and distortion performance of an ADC based on a fast-fourier transform (FFT) analysis. A brief introduction on the theory of signal-to-noise measurement with ADCs is provided at the end of this section.

For the test, two types of input signals were used:

  • A ultra-low noise DC source at 1.8 V
  • A 1-kHz sine wave, at an amplitude of 0.6 VPP, which represents low output of Sin/Cos encoders

The input signal is applied to one of the input channels A+, A– or B+, B– at a time, while the other channel while the other channel is unconnected. The purpose is to measure and highlight the ultra-low cross-talk level among the two channels A and B (or sine and cosine, respectively).

The DC input is used to ensure the best noise performance (since no noise comes from the input/source). The 1-kHz sine wave is used to measure the effective number of bits on the two parallel channels.

Both channels A and B were sampled at 32 kHz and 8192 consecutive 16-bit samples were acquired for each channel A and B. The DFT has been calculated for the collected data to measure the SNR and THD.

The results are presented in the following figures.

TIDA-00176 DFT of 16-Bit Channel A Output With 1.8-V DC at Input AFigure 7-4 DFT of 16-Bit Channel A Output With 1.8-V DC at Input A
TIDA-00176 DFT of 16-Bit Channel B Output With 1.8-V DC at Input BFigure 7-5 DFT of 16-Bit Channel B Output With 1.8-V DC at Input B

In the previous figures, the measured noise floor is below 120 dB, meaning this is the best performance that could be achieved. Also note that the plots are referred to the full scale input range, that is the maximum amplitude. 0 dB correspond to the maximum input possible for the ADS8354, which in this configuration would be 2 VPP.

The following figures show the DFT of the entire high-resolution channel with a sinusoidal input voltage of 0.6-VPP amplitude and 1 KHz. This equals around –6-dB input level versus the theoretical full scale range input.

The input signal was applied either to the channel A or channel B. The other channel was left open in order to measured cross-talk as well.

TIDA-00176 DFT of 16-Bit Channel A Output With 600-mVPP, 1-KHz Sine Wave Input Applied on Input AFigure 7-6 DFT of 16-Bit Channel A Output With 600-mVPP, 1-KHz Sine Wave Input Applied on Input A
TIDA-00176 DFT of 16-Bit Channel B Output With 600-mVPP, 1-KHz Sine Wave Input Applied on Input AFigure 7-7 DFT of 16-Bit Channel B Output With 600-mVPP, 1-KHz Sine Wave Input Applied on Input A
TIDA-00176 DFT of 16-Bit Channel B Output With 600-mVPP, 1-KHz Sine Wave Input Applied on Input BFigure 7-8 DFT of 16-Bit Channel B Output With 600-mVPP, 1-KHz Sine Wave Input Applied on Input B
TIDA-00176 DFT of 16-bit Channel A Output With 600-mVPP, 1-KHz Sine Wave Input Applied on Input BFigure 7-9 DFT of 16-bit Channel A Output With 600-mVPP, 1-KHz Sine Wave Input Applied on Input B

These figures are referred to the theoretical full scale input range. Note that the first and second harmonics of the 1-kHz sinusoidal signal are due to the signal source itself, (normally a very aggressive notch filter is used to isolate the frequency of the test signal; refer also to SLAU515 for example).

Also note that the 1-kHz signal has a slight spread in frequency. This is not due to the TIDA-00176 hardware but due to a jitter in the F28069 software implementation, which triggered the SPI transfer to start the ADS8354 conversion (hold-mode) with a jitter of one CPU clock cycle equivalent to 12.5 ns.

The previous pictures also highlighted that there is basically no cross-talk between the two analog channels for sine (signal A+, A–) and cosine (B+, B–). The spectrum (DFT) is half the sampling frequency (the second half of the spectrum is a specular copy of the first half, so it is not shown in the plots). The Hann function (http://en.wikipedia.org/wiki/Hann_function) is used for windowing the data to obtain cleaner plots in the frequency domain.

THD, SNR and ENOB versus the full-scale signal can then be calculated for this design and are listed in Table 7-2.

Table 7-2 High-Resolution Signal Path (THS4531A and ADS8354) Typical Performance
PARAMETERVALUE (MEASURED)
SNR89.1 dB
SINAD88.5 dB
ENOB14.4 bit
Cross-Talk–107 to –109 dB