TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL

In this section, the performance of the comparator with hysteresis that converts the single-ended analog signals A, B, and R into digital signals was tested.

The focus was on the propagation delay of the comparator output signals ATTL, BTTL, and RTTL at the host connector J6 versus the analog input at the ADS8354 for the high-resolution path as well as the single-ended analog signals for the analog path.

The aim of the test was to measure the overall signal delay of the comparator path versus the analog path, considering the delays introduced by hysteresis, phase shift due to low-pass filtering and the propagation delay of the comparator itself.

Since all three channels A, B, and R were done absolutely symmetrical with regards to the comparator output, measurements have only been conducted with channel A.

The analog signals were both measured with a single-ended probe, hence on the differential input of the ADS8354 only the positive differential signal was measured versus GND.

For the test sinusoidal input signals were injected at the encoder connector J9, A_P, A_M (sine) and B_P, B_M (cosine) as well as P_M and R_P.

For the high-resolution path, the amplitude was set to 1.0 VPP (typical) and 0.3 VPP (minimum) with 100 Hz and 500 kHz (maximum) to test the worst case scenario for the propagation delay. For analog path, the measurement was conducted at 0.3 VPP with 100 Hz and 500 kHz, as corner cases.

Test results are shown in the following figures. Note that both, the high-resolution path (at the differential input of the ADS8354) and the single-ended analog path (at connector J6.Pin 12) are compared versus the comparator output (at connector J6.Pin 18).

TIDA-00176 Comparator Output ATTL versus Differential Input to ADS8354 and Analog Output A (J6-12) With Input 1.0 VPP, 100 Hz at Encoder Connector J9-1, J9-2Figure 7-13 Comparator Output ATTL versus Differential Input to ADS8354 and Analog Output A (J6-12) With Input 1.0 VPP, 100 Hz at Encoder Connector J9-1, J9-2
TIDA-00176 Comparator Output ATTL versus Differential Input to ADS8354 and Analog Output A (J6-12) With Input 1.0 VPP, 500-kHz Encoder Connector J9-1, J9-2Figure 7-15 Comparator Output ATTL versus Differential Input to ADS8354 and Analog Output A (J6-12) With Input 1.0 VPP, 500-kHz Encoder Connector J9-1, J9-2
TIDA-00176 Comparator Output ATTL versus Differential Input to ADS8354 and Analog Output A (J6-12) With Input 0.3 VPP, 100 Hz at Encoder Connector J9-1, J9-2Figure 7-14 Comparator Output ATTL versus Differential Input to ADS8354 and Analog Output A (J6-12) With Input 0.3 VPP, 100 Hz at Encoder Connector J9-1, J9-2
TIDA-00176 Comparator Output ATTL versus Differential Input to ADS8354 and Analog Output A (J6-12) With Input 0.3 VPP, 500 kHz at Encoder Connector J9-1, J9-2Figure 7-16 Comparator Output ATTL versus Differential Input to ADS8354 and Analog Output A (J6-12) With Input 0.3 VPP, 500 kHz at Encoder Connector J9-1, J9-2

As expected, the maximum overall phase shift including RC filter decoupling networks occurs at 500 kHz with the lowest input amplitude and is total around 320 ns, equal to 57 degrees, which is well below 90 degree and within the 60 degree the specification per Section 2. The very low propagation delay of the TLV3201 with typically 40 ns has a major impact on this low number. This also gives a major margin to compensate all the possible spreads in the parameters influencing the amount of phase delay like due to low-pass filters, and so on.

The propagation delay at 100 Hz is almost the same than for the high-resolution channel because the delay at lower frequencies is dominated by the amplitude-dependent hysteresis.

On the single-ended analog path, there’s almost no delay at 500 kHz despite a 250-ns propagation delay of the comparator with hysteresis itself. This is due to the strong low-pass filter at the single-ended analog output (R = 100 Ω, C = 4.7 nF) to drive an embedded switched capacitor ADC like in the Piccolo MCU. This frequency depended phase delay slightly compensates the delay from the comparator at higher frequencies.

In a second step, only the delay related to the comparator with hysteresis was measured. The delay was specified as the input to the comparator (analog signal at R50) and the output of the comparator. Note that 0.3 VPP at the encoder input equals around 0.5 VPP at the comparator input due to the previous amplifier stage with gain of 1.66.

The delay introduced by the comparator block only (hysteresis and comparator propagation delay) has been measured and is listed in Table 7-3.

Table 7-3 Hysteresis Comparator Subsystem Delay
INPUT AT ENCODER CONNECTORVOLTAGE AT COMPARATOR INPUT (FOR EXAMPLE, R50)PROPAGATION DELAYPHASE DELAY
1.0 VPP, 100 Hz1.66 V170 µs6.1 degrees
0.3 VPP, 100 Hz0.5 V560 µs20.1 degrees
1.0 VPP, 500 kHz1.52 V120 ns21 degrees
0.3 VPP, 500 kHz0.46 V200 ns36 degrees

The difference to the overall delay in Figure 7-13 to Figure 7-16 is to the low-pass noise filter in the analog path, which contributes to around further 22 degrees at 500 kHz for the high-resolution signal path. However, the delay is still well below 90 degrees.

If an ideal phase matching is desired, a corresponding low-pass filter can be implemented with the THS4531A as outlined in Section 4.5.