TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

7.5.3 IEC-61000-4-4 EFT Test Results

A picture of the EFT test setup for TIDA-00176 is shown in Figure 7-39. During the EFT test, the SubD-15 female connector was connected to a 30-m (10 m + 20 m) twisted pair shielded cable with a ROD480 Sin/Cos encoder at the far end.

TIDA-00176 IEC61000-4-4 EFT Test Setup for TIDA-00176 (Right Side on Top, Left Side on Bottom) Figure 7-39 IEC61000-4-4 EFT Test Setup for TIDA-00176 (Right Side on Top, Left Side on Bottom)
Table 7-12 IEC-61000-4-4 EFT Test Results for TIDA-00176
PHENOMENON BASIC STANDARD LEVEL TIDA-00176 CONNECTOR ACHIEVED PERFORMANCE CRITERION(1) COMMENT
EFT IEC61000-4-4 ±2 kV/5 kHz, capacitive clamp SubD-15 B
EFT IEC61000-4-4 ±2 kV/5 kHz, capacitive clamp SubD-15 B
EFT IEC61000-4-4 ±4 kV/5 kHz, capacitive clamp SubD-15 B Not required per IEC61800-3
EFT IEC61000-4-4 ±4 kV/5 kHz, capacitive clamp SubD-15 B Not required per IEC61800-3
(1) At least Class B was achieved because any angle measured during the ESD test did not deviate more than 0.045 degrees from the reference angle. For class A, see Table 7-7, note 1).
Table 7-13 IEC-61000-4-4 EFT Angle Error Distribution During Entire Test
ERROR COUNTER ANGULAR ERROR RANGE (DEGREE) OCCURRENCE @ 2-kV EFT OCCURRENCE @ 4-kV EFT
Error Range 1 >1.0 0 0
Error Range 2 0.18 ≤ Error < 1.0 0 0
Error Range 3 0.1 ≤ Error < 0.18 0 0
Error Range 4 0.01 ≤ Error < 0.1 254 1302
Error Range 5 0.001 ≤ Error < 0.01 1658 3413
TIDA-00176 Measured Angle During ±2-kV EFT Test Period at 10-Hz Update Rate Figure 7-40 Measured Angle During ±2-kV EFT Test Period at 10-Hz Update Rate

The angle remains constant prior, during, and after the EFT test at 2 kV. The maximum error on the plot is 0.003 degrees. As the update rate is only 10 Hz (due to 115000-baud UART), the angle is higher than the 0.001-degree error that likely occurred in between and were not printed. Note that the error counters are updated at 16 kHz.