TIDUA05B June   2015  – March 2025

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 System Description
    1. 1.1 Design Overview
    2. 1.2 Analog Sin/Cos Incremental Encoder
      1. 1.2.1 Sin/Cos Encoder Output Signals
      2. 1.2.2 Sin/Cos Encoder Electrical Parameter Examples
    3. 1.3 Method to Calculate High-Resolution Position With Sin/Cos Encoders
      1. 1.3.1 Theoretical Approach
        1. 1.3.1.1 Overview
        2. 1.3.1.2 Coarse Resolution Angle Calculation
        3. 1.3.1.3 Fine Resolution Angle Calculation
        4. 1.3.1.4 Interpolated High-Resolution Angle Calculation
        5. 1.3.1.5 Practical Implementaion for Non-Ideal Synchronization
        6. 1.3.1.6 Resolution, Accuracy, and Speed Considerations
    4. 1.4 Sin/Cos Encoder Parameters Impact on Analog Circuit Specification
      1. 1.4.1 Analog Signal Chain Design Consideration for Phase Interpolation
      2. 1.4.2 Comparator Function System Design for Incremental Count
  8. 2 Design Features
    1. 2.1 Sin/Cos Encoder Interface
    2. 2.2 Host Processor Interface
    3. 2.3 Evaluation Firmware
    4. 2.4 Power Management
    5. 2.5 EMC Immunity
  9. 3 Block Diagram
  10. 4 Circuit Design and Component Selection
    1. 4.1 Analog Signal Chain
      1. 4.1.1 High-Resolution Signal Path With 16-Bit Dual Sampling ADC
        1. 4.1.1.1 Component Selection
        2. 4.1.1.2 Input Signal Termination and Protection
        3. 4.1.1.3 Differential Amplifier THS4531A and 16-Bit ADC ADS8354
      2. 4.1.2 Analog Signal Path With Single-Ended Output for MCU With Embedded ADC
      3. 4.1.3 Comparator Subsystem for Digital Signals A, B, and R
        1. 4.1.3.1 Non-Inverting Comparator With Hysteresis
    2. 4.2 Power Management
      1. 4.2.1 24-V Input to 6-V Intermediate Rail
      2. 4.2.2 Encoder Supply
      3. 4.2.3 Signal Chain Power Supply 5 V and 3.3 V
    3. 4.3 Host Processor Interface
      1. 4.3.1 Signal Description
      2. 4.3.2 High-Resolution Path Using 16-Bit Dual ADC ADS8354 With Serial Output
        1. 4.3.2.1 ADS8354 Input Full Scale Range Output Data Format
        2. 4.3.2.2 ADS8354 Serial Interface
        3. 4.3.2.3 ADS8354 Conversion Data Read
        4. 4.3.2.4 ADS8354 Register Configuration
    4. 4.4 Encoder Connector
    5. 4.5 Design Upgrades
  11. 5 Software Design
    1. 5.1 Overview
    2. 5.2 C2000 Piccolo Firmware
    3. 5.3 User Interface
  12. 6 Getting Started
    1. 6.1 TIDA-00176 PCB Overview
    2. 6.2 Connectors and Jumper Settings
      1. 6.2.1 Connector and Jumpers Overview
      2. 6.2.2 Default Jumper Configuration
    3. 6.3 Design Evaluation
      1. 6.3.1 Prerequisites
      2. 6.3.2 Hardware Setup
      3. 6.3.3 Software Setup
      4. 6.3.4 User Interface
  13. 7 Test Results
    1. 7.1 Analog Performance Tests
      1. 7.1.1 High-Resolution Signal Path
        1. 7.1.1.1 Bode Plot of Analog Path from Encoder Connector to ADS8354 Input
        2. 7.1.1.2 Performance Plots (DFT) for Entire High-Resulation Signal Path
        3. 7.1.1.3 Background on AC Performance Definitions With ADCs
      2. 7.1.2 Differential to Single-Ended Analog Signal Path
      3. 7.1.3 Comparator Subsystem With Digital Output Signals ATTL, BTTL, and RTTL
    2. 7.2 Power Supply Tests
      1. 7.2.1 24-V DC/DC Input Supply
        1. 7.2.1.1 Load-Line Regulation
        2. 7.2.1.2 Output Voltage Ripple
        3. 7.2.1.3 Switching Node and Switching Frequency
        4. 7.2.1.4 Efficiency
        5. 7.2.1.5 Bode Plot
        6. 7.2.1.6 Thermal Plot
      2. 7.2.2 Encoder Power Supply Output Voltage
      3. 7.2.3 5-V and 3.3-V Point-of-Load
    3. 7.3 System Performance
      1. 7.3.1 Sin/Cos Encoder Output Signal Emulation
        1. 7.3.1.1 One Period (Incremental Phase) Test
        2. 7.3.1.2 One Mechanical Revolution Test at Maximum Speed
    4. 7.4 Sin/Cos Encoder System Tests
      1. 7.4.1 Zero Index Marker R
      2. 7.4.2 Functional System Tests
    5. 7.5 EMC Test Result
      1. 7.5.1 Test Setup
      2. 7.5.2 IEC-61000-4-2 ESD Test Results
      3. 7.5.3 IEC-61000-4-4 EFT Test Results
      4. 7.5.4 IEC-61000-4-5 Surge Test Results
  14. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 PCB Layout Guidelines
      1. 8.3.1 PCB Layer Plots
    4. 8.4 Altium Project
    5. 8.5 Gerber Files
    6. 8.6 Software Files
  15. 9 References
  16. 10About the Author
    1.     Recognition
  17. 11Revision History

7.3.1.1 One Period (Incremental Phase) Test

The first tests showed that the error injected by the dual output signal generator was much worse than the TIDA-00176 accuracy, spoiling completely the purpose of the tests. Noise and error sources for could be "briefly" summarized as:

  • Gain error (amplitude of A not equal to the amplitude of B)
  • Phase shift error (not exactly 90 degrees constant as expected)
  • Offset error (average of A or B signal is not equal to 0)
  • HF noise due to the quantization error of the function generator
  • Frequency error (frequency of A not equal to the B one, even if the signal are "coupled")

CAUTION:

To reduce the quantization error and noise introduced by the function generator a 1-K to 1-µF LP filter is inserted between the signal generator and the
TIDA-00176 inputs (the 1-K resistor is actually a series of two 500-Ω resistors to keep the network balanced) on the input.

To eliminate gain, offset, phase shift and frequency error between the two channels the following setup was applied: Only one output signal, filtered as described above was applied to both inputs A and B at the encoder connector J8 of the TIDA-00176, hence feeding with the same signal. This will eliminate the limitation of the function generator. Furthermore, any mismatch amongst the two channels of the ADS8354 (and their respective signal conditioning paths) can be better evaluated.

Indeed, the data acquired from the ADS8354 should show (in ideal world) two streams of raw identical data, while any mismatch at this level comes from the mismatch of the two channels, and not from the input itself. This can be also used to calibrate the system, since offset and gain error corrections could be performed to completely balance the A and B channels.

The data has been acquired at a 32-kHz sample rate using the F28069M LaunchPad connected to the TIDA-00176, as outlined in Section 6.

After the ADS8354 channel A and B data has been acquired by the F28069M, the 16-bit raw data has been dumped into an Excel file. Then the raw data for channel B has been exactly phase shifted by
90 degrees. After that the phase has been calculated using the inverse tangent of the raw data A and 90-degree phase shifted raw data B.

This test has been repeated for the 1.0-VPP amplitude and frequencies of 10 Hz up to 500 Hz. The result is shown in the following figures.

TIDA-00176 Phase Error over One Signal Period when 1.0-VPP 10-Hz Input is AppliedFigure 7-25 Phase Error over One Signal Period when 1.0-VPP 10-Hz Input is Applied

Within one incremental line (one signal period = 360 degrees), the phase error remains well within ±0.02 degrees. This corresponds to an error ±0.02/360 = 0.0055%. With respect to 16-bit resolution, this equals around ±3 LSB only.

The noise distribution is even within ±0.01 (±1.5 LSB). The phase error with the double period is due to a non-ideal 90-degree phase shift between the two signals A and B, as outlined in Section 1.

Note that an error of ±0.02 degrees over one signal period will correspond to a total error of ±10 micro-degrees (0.036 arc seconds) for an encoder with 2000 line counts.

The same tests have been performed in the thermal chamber at nominal 70°C to evaluate the system performance drift and, in particular, the absolute error on the angular position.

Again the double frequency modulation comes from the non-perfect matching (90-degree phase shift, and so on) of the two-input signal.

TIDA-00176 Phase Error at 70°C Over One Signal Period When 1.0-VPP 10-Hz Input is AppliedFigure 7-26 Phase Error at 70°C Over One Signal Period When 1.0-VPP 10-Hz Input is Applied

The same test was applied with a 0.6-VPP input in which the higher noise / lower SNR conditions are visible:

TIDA-00176 Phase Error at 23°C Ambient Over One Signal Period When 0.6-VPP 10-Hz Input is AppliedFigure 7-27 Phase Error at 23°C Ambient Over One Signal Period When 0.6-VPP 10-Hz Input is Applied
TIDA-00176 Phase Error at 70°C Ambient Over One Signal Period (One Revolution/2000) When 0.6-VPP 10-Hz Input is AppliedFigure 7-28 Phase Error at 70°C Ambient Over One Signal Period (One Revolution/2000) When 0.6-VPP 10-Hz Input is Applied

The ultra-low drift versus temperature is aligned to the expectation, also because of the characteristics of the selected op-amps and matched resistors used for the analog signal conditioning.