SLYY234 December 2024 AMC0106M05 , AMC0106M25 , AMC0136 , AMC0311D , AMC0311S , AMC0386 , AMC0386-Q1 , AMC1100 , AMC1106M05 , AMC1200 , AMC1200-Q1 , AMC1202 , AMC1203 , AMC1204 , AMC1211-Q1 , AMC1300 , AMC1300B-Q1 , AMC1301 , AMC1301-Q1 , AMC1302-Q1 , AMC1303M2510 , AMC1304L25 , AMC1304M25 , AMC1305M25 , AMC1305M25-Q1 , AMC1306M05 , AMC1306M25 , AMC1311 , AMC1311-Q1 , AMC131M03 , AMC1336 , AMC1336-Q1 , AMC1350 , AMC1350-Q1 , AMC23C12 , AMC3301 , AMC3330 , AMC3330-Q1
A reference layout is made for this circuit with an active area of 26 mm x 8.4 mm on a four-layer PCB.
With careful layout design placing the gate driver and the comparator on the opposite sides of the PCB, a smaller form factor is achieved, compared to a 16-pin smart gate driver's, taking advantage of their smaller package lengths. In comparison, a typical layout of ISO5451, a smart gate driver with CMOS input in a SOIC 16 package, has an active area of 20.83 mm x 12.95 mm on the PCB[10], as shown in Figure 123, which is about 23.5% bigger than the proposed design of UCC23513 and AMC23C11 in Figure 122.