SLYY234 December 2024 AMC0106M05 , AMC0106M25 , AMC0136 , AMC0311D , AMC0311S , AMC0386 , AMC0386-Q1 , AMC1100 , AMC1106M05 , AMC1200 , AMC1200-Q1 , AMC1202 , AMC1203 , AMC1204 , AMC1211-Q1 , AMC1300 , AMC1300B-Q1 , AMC1301 , AMC1301-Q1 , AMC1302-Q1 , AMC1303M2510 , AMC1304L25 , AMC1304M25 , AMC1305M25 , AMC1305M25-Q1 , AMC1306M05 , AMC1306M25 , AMC1311 , AMC1311-Q1 , AMC131M03 , AMC1336 , AMC1336-Q1 , AMC1350 , AMC1350-Q1 , AMC23C12 , AMC3301 , AMC3330 , AMC3330-Q1
Figure 150 shows the first compensation method, where an additional phase locked clock signal with a software configurable phase delay is used. For this compensation method the phase-shifted clock signal CLKOUT_delay is used as the clock input to SD0_CLK of the Sigma-Delta Filter Module (SDFM). For other types of Delta-Sigma Modulators and MCUs e.g. C2000 MCUs, the compensation method follows the same principle.
The implementation of a second phase-shifted clock signal offers the highest degree of freedom and user configurability. This means that various values for minimum hold time th(MIN) of various isolated modulators can be compensated by a simple change to the phase-shift value in software. The clock signals rising edge at the SD0_CLK input is phase-shifted such that the clocking signal complies with the data sampling point of the SDFM, as shown in Figure 151. The AM243x PRU_ICSSG PRU Timing Requirements in Sigma Delta Mode are 10 ns for minimum setup time tsu (SD_D-SD_CLK) (MIN) = 10 ns and 5 ns for minimum hold time th(SD_CLK-SD_D) (MIN) = 5 ns. This creates a need for compensation to maintain correct acquisition at the data input SDx_D with reference to the rising clock edge of the SDx_CLK signal as the AMC1306M25 minimum hold time th(MIN) is 3.5 ns, but 5 ns can be required. After this compensation method is applied, the 10-ns minimum setup and 5-ns hold timings for the Sigma Delta Mode of the AM243x PRU_ICSSG PRU timing requirements are met, see Figure 151.