SLYY234 December 2024 AMC0106M05 , AMC0106M25 , AMC0136 , AMC0311D , AMC0311S , AMC0386 , AMC0386-Q1 , AMC1100 , AMC1106M05 , AMC1200 , AMC1200-Q1 , AMC1202 , AMC1203 , AMC1204 , AMC1211-Q1 , AMC1300 , AMC1300B-Q1 , AMC1301 , AMC1301-Q1 , AMC1302-Q1 , AMC1303M2510 , AMC1304L25 , AMC1304M25 , AMC1305M25 , AMC1305M25-Q1 , AMC1306M05 , AMC1306M25 , AMC1311 , AMC1311-Q1 , AMC131M03 , AMC1336 , AMC1336-Q1 , AMC1350 , AMC1350-Q1 , AMC23C12 , AMC3301 , AMC3330 , AMC3330-Q1
A compromise to meet the MCUs timing requirements is to reduce the modulator clock frequency. In this example a 17 MHz clock frequency allows the setup and hold timing requirements of the MCU to be met. The calculated setup and hold times including minimum and maximum values at a clock frequency of 17 MHz are shown in Table 27. The margin for the minimum setup time to the MCUs setup time requirement is 0 ns. This means tolerances in the system can possibly lead to incorrect acquisition of data. A larger margin for tolerances in the system can be achieved by further reducing the clock frequency, but this has a negative effect on the system performance.
| Min. Setup Time @MCU | 10.0 ns |
| Max. Setup Time @MCU | 27.7 ns |
| Min. Hold Time @MCU | 31.1 ns |
| Max. Hold Time @MCU | 48.8 ns |