SPRUJ79 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 â–º C29x SYSTEM RESOURCES
    1.     Technical Reference Manual Overview
  4. 2 F29x Processor
    1. 2.1 CPU Architecture
      1. 2.1.1 C29x Related Collateral
    2. 2.2 Lock and Commit Registers
    3. 2.3 C29x CPU Registers
      1. 2.3.1 C29CPU Base Address Table
      2. 2.3.2 C29_RTINT_STACK Registers
      3. 2.3.3 C29_SECCALL_STACK Registers
      4. 2.3.4 C29_SECURE_REGS Registers
      5. 2.3.5 C29_DIAG_REGS Registers
      6. 2.3.6 C29_SELFTEST_REGS Registers
  5. 3 System Control and Interrupts
    1. 3.1  C29x System Control Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1 Reset Sources
      2. 3.3.2 External Reset (XRS)
      3. 3.3.3 Simulate External Reset
      4. 3.3.4 Power-On Reset (POR)
      5. 3.3.5 Debugger Reset (SYSRS)
      6. 3.3.6 Watchdog Reset (WDRS)
      7. 3.3.7 ESM NMI Watchdog Reset (NMIWDRS)
      8. 3.3.8 EtherCAT Slave Controller (ESC) Module Reset Output
    4. 3.4  Safety Features
      1. 3.4.1 Write Protection on Registers
        1. 3.4.1.1 LOCK Protection on System Configuration Registers
        2. 3.4.1.2 EALLOW Protection
      2. 3.4.2 PIPE Vector Address Validity Check
      3. 3.4.3 NMIWDs
      4. 3.4.4 System Control Registers Parity Protection
      5. 3.4.5 ECC Enabled RAMs, Shared RAMs Protection
      6. 3.4.6 ECC Enabled Flash Memory
      7. 3.4.7 ERRORSTS Pin
    5. 3.5  Clocking
      1. 3.5.1 Clock Sources
        1. 3.5.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.5.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.5.1.3 External Oscillator (XTAL)
        4. 3.5.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.5.2 Derived Clocks
        1. 3.5.2.1 Oscillator Clock (OSCCLK)
        2. 3.5.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.5.3 Device Clock Domains
        1. 3.5.3.1 System Clock (PLLSYSCLK)
        2. 3.5.3.2 CPU Clock (CPUCLK)
        3. 3.5.3.3 Peripheral Clock (PERx.SYSCLK)
        4. 3.5.3.4 MCAN Bit Clock
        5. 3.5.3.5 CPU Timer2 Clock (TIMER2CLK)
      4. 3.5.4 External Clock Output (XCLKOUT)
      5. 3.5.5 Clock Connectivity
      6. 3.5.6 Using an External Crystal or Resonator
        1. 3.5.6.1 X1/X2 Precondition Circuit
      7. 3.5.7 PLL
        1. 3.5.7.1 System Clock Setup
        2. 3.5.7.2 SYS PLL Bypass
      8. 3.5.8 Clock (OSCCLK) Failure Detection
        1. 3.5.8.1 Missing Clock Detection Logic
        2. 3.5.8.2 Dual Clock Comparator (DCC)
    6. 3.6  Bus Architecture
      1. 3.6.1 Safe Interconnect
        1. 3.6.1.1 Safe Interconnect for Read Operation
        2. 3.6.1.2 Safe Interconnect for Write Operation
      2. 3.6.2 Peripheral Access Configuration using FRAMESEL
      3. 3.6.3 Bus Arbitration
    7. 3.7  32-Bit CPU Timers 0/1/2
    8. 3.8  Watchdog Timers
      1. 3.8.1 Servicing the Watchdog Timer
      2. 3.8.2 Minimum Window Check
      3. 3.8.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.8.4 Watchdog Operation in Low-Power Modes
      5. 3.8.5 Emulation Considerations
    9. 3.9  Low-Power Modes
      1. 3.9.1 IDLE
      2. 3.9.2 STANDBY
    10. 3.10 Memory Subsystem (MEMSS)
      1. 3.10.1 Introduction
      2. 3.10.2 Features
      3. 3.10.3 Configuration Bits
        1. 3.10.3.1 Memory Initialization
      4. 3.10.4 RAM
        1. 3.10.4.1  MEMSS Architecture
        2. 3.10.4.2  RAM Memory Controller Overview
        3. 3.10.4.3  Memory Controllers
          1. 3.10.4.3.1 128-Bit LPx and CPx Memory Controller
          2. 3.10.4.3.2 64-Bit LDx and CDx Memory Controller
          3. 3.10.4.3.3 M0 Memory Controller
        4. 3.10.4.4  RTDMA Burst Support
        5. 3.10.4.5  Atomic Memory Operations
        6. 3.10.4.6  RAM ECC
        7. 3.10.4.7  Read-Modify-Write Operations
        8. 3.10.4.8  Dataline Buffer
        9. 3.10.4.9  HSM Sync Bridge
        10. 3.10.4.10 Access Bridges
          1. 3.10.4.10.1 Debug Access Bridge
          2. 3.10.4.10.2 Global Access Bridge
          3. 3.10.4.10.3 Program Access Bridge
      5. 3.10.5 ROM
        1. 3.10.5.1 ROM Dataline Buffer
        2. 3.10.5.2 ROM Prefetch
      6. 3.10.6 Arbitration
      7. 3.10.7 Test Modes
      8. 3.10.8 Emulation Mode
    11. 3.11 System Control Register Configuration Restrictions
    12. 3.12 Software
      1. 3.12.1  SYSCTL Registers to Driverlib Functions
      2. 3.12.2  MEMSS Registers to Driverlib Functions
      3. 3.12.3  CPU Registers to Driverlib Functions
      4. 3.12.4  WD Registers to Driverlib Functions
      5. 3.12.5  CPUTIMER Registers to Driverlib Functions
      6. 3.12.6  XINT Registers to Driverlib Functions
      7. 3.12.7  LPOST Registers to Driverlib Functions
      8. 3.12.8  SYSCTL Examples
        1. 3.12.8.1 Missing clock detection (MCD) - SINGLE_CORE
        2. 3.12.8.2 XCLKOUT (External Clock Output) Configuration - SINGLE_CORE
      9. 3.12.9  TIMER Examples
        1. 3.12.9.1 Timer Academy Lab - SINGLE_CORE
        2. 3.12.9.2 CPU Timers - SINGLE_CORE
        3. 3.12.9.3 CPU Timers - SINGLE_CORE
      10. 3.12.10 WATCHDOG Examples
        1. 3.12.10.1 Watchdog - SINGLE_CORE
      11. 3.12.11 LPM Examples
        1. 3.12.11.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO - SINGLE_CORE
        2. 3.12.11.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog - SINGLE_CORE
        3. 3.12.11.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO - SINGLE_CORE
        4. 3.12.11.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog - SINGLE_CORE
    13. 3.13 SYSCTRL Registers
      1. 3.13.1  SYSCTRL Base Address Table
      2. 3.13.2  DEV_CFG_REGS Registers
      3. 3.13.3  MEMSS_L_CONFIG_REGS Registers
      4. 3.13.4  MEMSS_C_CONFIG_REGS Registers
      5. 3.13.5  MEMSS_M_CONFIG_REGS Registers
      6. 3.13.6  MEMSS_MISCI_REGS Registers
      7. 3.13.7  CPU_SYS_REGS Registers
      8. 3.13.8  CPU_PER_CFG_REGS Registers
      9. 3.13.9  WD_REGS Registers
      10. 3.13.10 CPUTIMER_REGS Registers
      11. 3.13.11 XINT_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Device Boot Flow
      2. 4.5.2 CPU1 Boot Flow
      3. 4.5.3 Emulation Boot Flow
      4. 4.5.4 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 MPOST and LPOST Configurations
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Memory Maps
        1. 4.7.4.1 Boot ROM Memory-Maps
        2. 4.7.4.2 Reserved RAM Memory-Maps
      5. 4.7.5  ROM Structure and Status Information
      6. 4.7.6  Boot Modes and Loaders
        1. 4.7.6.1 Boot Modes
          1. 4.7.6.1.1 Flash Boot
          2. 4.7.6.1.2 RAM Boot
          3. 4.7.6.1.3 Wait Boot
        2. 4.7.6.2 Bootloaders
          1. 4.7.6.2.1 SPI Boot Mode
          2. 4.7.6.2.2 I2C Boot Mode
          3. 4.7.6.2.3 Parallel Boot Mode
          4. 4.7.6.2.4 CAN Boot Mode
          5. 4.7.6.2.5 CAN-FD Boot Mode
          6. 4.7.6.2.6 UART Boot Mode
      7. 4.7.7  GPIO Assignments
      8. 4.7.8  HSM and C29 ROM Task Ownership and Interactions
        1. 4.7.8.1 Application Authentication by HSM
      9. 4.7.9  Boot Status Information
        1. 4.7.9.1 Booting Status
      10. 4.7.10 BootROM Timing
    8. 4.8 Software
      1. 4.8.1 BOOT Examples
  7. 5 Lockstep Compare Module (LCM)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
      3. 5.1.3 Lockstep Compare Modules
    2. 5.2 Enabling LCM Comparators
    3. 5.3 LCM Redundant Module Configuration
    4. 5.4 LCM Error Handling
    5. 5.5 Debug Mode with LCM
    6. 5.6 Register Parity Error Protection
    7. 5.7 Functional Logic
      1. 5.7.1 Comparator Logic
      2. 5.7.2 Self-Test Logic
        1. 5.7.2.1 Match Test Mode
        2. 5.7.2.2 Mismatch Test Mode
      3. 5.7.3 Error Injection Tests
        1. 5.7.3.1 Comparator Error Force Test
        2. 5.7.3.2 Register Parity Error Test
    8. 5.8 Software
      1. 5.8.1 LCM Registers to Driverlib Functions
    9. 5.9 LCM Registers
      1. 5.9.1 LCM Base Address Table
      2. 5.9.2 LCM_REGS Registers
  8. 6 Peripheral Interrupt Priority and Expansion (PIPE)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 Interrupt Concepts
      3. 6.1.3 PIPE Related Collateral
    2. 6.2 Interrupt Architecture
      1. 6.2.1 Dynamic Priority Arbitration Block
      2. 6.2.2 Post Processing Block
      3. 6.2.3 Memory-Mapped Registers
    3. 6.3 Interrupt Propagation
    4. 6.4 Configuring Interrupts
      1. 6.4.1 Enabling and Disabling Interrupts
      2. 6.4.2 Prioritization
        1. 6.4.2.1 User-Configured Interrupt Priority
        2. 6.4.2.2 Index-Based Fixed Interrupt Priority
      3. 6.4.3 Nesting and Priority Grouping
      4. 6.4.4 Stack Protection
      5. 6.4.5 Context
    5. 6.5 Safety and Security
      1. 6.5.1 Access Control
      2. 6.5.2 PIPE Errors
      3. 6.5.3 Register Data Integrity and Safety
      4. 6.5.4 Self-Test and Diagnostics
    6. 6.6 Software
      1. 6.6.1 PIPE Registers to Driverlib Functions
      2. 6.6.2 INTERRUPT Examples
        1. 6.6.2.1 RTINT vs INT Latency example - SINGLE_CORE
        2. 6.6.2.2 INT and RTINT Nesting Example - SINGLE_CORE
    7. 6.7 PIPE Registers
      1. 6.7.1 PIPE Base Address Table
      2. 6.7.2 PIPE_REGS Registers
  9. 7  Error Signaling Module (ESM_C29)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 ESM Related Collateral
    2. 7.2 ESM Subsystem
      1. 7.2.1 System ESM
        1. 7.2.1.1 Error Pin Monitor Event
      2. 7.2.2 Safety Aggregator
        1. 7.2.2.1 EDC Controller Interface Description
          1. 7.2.2.1.1 EDC_REGS Registers
        2. 7.2.2.2 Read Operation on EDC Controller
        3. 7.2.2.3 Write Operation on EDC Controller
        4. 7.2.2.4 Safety Aggregator Error Injection
      3. 7.2.3 ESM Subsystem Integration View
    3. 7.3 ESM Functional Description
      1. 7.3.1 Error Event Inputs
      2. 7.3.2 Error Interrupt Outputs
        1. 7.3.2.1 High Priority Watchdog
        2. 7.3.2.2 Critical Priority Interrupt Output
      3. 7.3.3 Error Pin Output (ERR_O/ERRORSTS)
        1. 7.3.3.1 Minimum Time Interval
        2. 7.3.3.2 PWM Mode
      4. 7.3.4 Reset Type Information for ESM Registers
      5. 7.3.5 Clock Stop
      6. 7.3.6 Commit/Lock for MMRs
      7. 7.3.7 Safety Protection for MMRs
      8. 7.3.8 Register Configuration Tieoffs
        1. 7.3.8.1 Group0 High Priority Tieoff
        2. 7.3.8.2 High Priority Watchdog Enable Tieoff
    4. 7.4 ESM Configuration Guide
    5. 7.5 Interrupt Condition Control and Handling
      1. 7.5.1 ESM Low Priority Error Interrupt
      2. 7.5.2 ESM High Priority Error Interrupt
      3. 7.5.3 Critical Priority Error Interrupt
      4. 7.5.4 High Priority Watchdog Interrupt
      5. 7.5.5 Safety Aggregator Interrupt Control and Handling
    6. 7.6 Software
      1. 7.6.1 ESM_CPU Registers to Driverlib Functions
      2. 7.6.2 ESM_SYS Registers to Driverlib Functions
      3. 7.6.3 ESM_SAFETY_AGGREGATOR Registers to Driverlib Functions
      4. 7.6.4 ESM Examples
        1. 7.6.4.1 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        2. 7.6.4.2 ESM Multicore Example (CPU1,CPU3) - MULTI_CORE
        3. 7.6.4.3 ESM - SINGLE_CORE
        4. 7.6.4.4 ESM - SINGLE_CORE
    7. 7.7 ESM Registers
      1. 7.7.1 ESM Base Address Table
      2. 7.7.2 ESM_CPU_REGS Registers
      3. 7.7.3 ESM_SYSTEM_REGS Registers
      4. 7.7.4 ESM_SAFETYAGG_REGS Registers
  10. 8  Error Aggregator
    1. 8.1 Introduction
    2. 8.2 Error Aggregator Modules
    3. 8.3 Error Propagation Path from Source to CPU
    4. 8.4 Error Aggregator Interface
      1. 8.4.1 Functional Description
    5. 8.5 Error Condition Handling User Guide
    6. 8.6 Error Type Information
    7. 8.7 Error Sources Information
    8. 8.8 Software
      1. 8.8.1 ERROR_AGGREGATOR Registers to Driverlib Functions
    9. 8.9 ERRORAGGREGATOR Registers
      1. 8.9.1 ERRORAGGREGATOR Base Address Table
      2. 8.9.2 HSM_ERROR_AGGREGATOR_CONFIG_REGS Registers
      3. 8.9.3 ERROR_AGGREGATOR_CONFIG_REGS Registers
  11. 9 Flash Module
    1. 9.1 Introduction to Flash Memory
      1. 9.1.1 FLASH Related Collateral
      2. 9.1.2 Features
      3. 9.1.3 Flash Tools
      4. 9.1.4 Block Diagram
    2. 9.2 Flash Subsystem Overview
    3. 9.3 Flash Banks and Pumps
    4. 9.4 Flash Read Interfaces
      1. 9.4.1 Bank Modes and Swapping
      2. 9.4.2 Flash Wait States
      3. 9.4.3 Buffer and Cache Mechanisms
        1. 9.4.3.1 Prefetch Mechanism and Block Cache
        2. 9.4.3.2 Data Line Buffer
        3. 9.4.3.3 Sequential Data Pre-read Mode
      4. 9.4.4 Flash Read Arbitration
      5. 9.4.5 Error Correction Code (ECC) Protection
      6. 9.4.6 Procedure to Change Flash Read Interface Registers
    5. 9.5 Flash Erase and Program
      1. 9.5.1 Flash Semaphore and Update Protection
      2. 9.5.2 Erase
      3. 9.5.3 Program
    6. 9.6 Migrating an Application from RAM to Flash
    7. 9.7 Flash Registers
      1. 9.7.1 FLASH Base Address Table
      2. 9.7.2 FLASH_CMD_REGS_FLC1 Registers
      3. 9.7.3 FLASH_CMD_REGS_FLC2 Registers
      4. 9.7.4 FRI_CTRL_REGS Registers
  12. 10Safety and Security Unit (SSU)
    1. 10.1  Introduction
      1. 10.1.1 SSU Related Collateral
      2. 10.1.2 Block Diagram
      3. 10.1.3 System SSU Configuration Example
    2. 10.2  Access Protection Ranges
      1. 10.2.1 Access Protection Inheritance
    3. 10.3  LINKs
    4. 10.4  STACKs
    5. 10.5  ZONEs
    6. 10.6  SSU-CPU Interface
      1. 10.6.1 SSU Operation in Lockstep Mode
    7. 10.7  SSU Operation Modes
    8. 10.8  Security Configuration and Flash Management
      1. 10.8.1 BANKMGMT Sectors
      2. 10.8.2 SECCFG Sectors
      3. 10.8.3 SECCFG Sector Address Mapping
      4. 10.8.4 SECCFG Sector Memory Map
      5. 10.8.5 SECCFG CRC
    9. 10.9  Flash Write/Erase Access Control
      1. 10.9.1 Permanent Flash Lock (Write/Erase Protection)
      2. 10.9.2 Updating Flash MAIN Sectors
      3. 10.9.3 Firmware-Over-The-Air Updates (FOTA)
      4. 10.9.4 Updating Flash SECCFG Sectors
      5. 10.9.5 Reading Flash SECCFG Sectors
    10. 10.10 RAMOPEN Feature
    11. 10.11 Debug Authorization
      1. 10.11.1 Global CPU Debug Enable
      2. 10.11.2 ZONE Debug
      3. 10.11.3 Authentication for Debug Access
        1. 10.11.3.1 Password-based Authentication
        2. 10.11.3.2 CPU-based Authentication
    12. 10.12 Hardcoded Protections
    13. 10.13 SSU Register Access Permissions
      1. 10.13.1 Permissions for SSU General Control Registers
      2. 10.13.2 Permissions for SSU CPU1 Configuration Registers
      3. 10.13.3 Permissions for SSU CPU2+ Configuration Registers
      4. 10.13.4 Permissions for CPU1 Access Protection Registers
      5. 10.13.5 Permissions for CPU2+ Access Protection Registers
    14. 10.14 SSU Fault Signals
    15. 10.15 Software
      1. 10.15.1 SSU Registers to Driverlib Functions
    16. 10.16 SSU Registers
      1. 10.16.1 SSU Base Address Table
      2. 10.16.2 SSU_GEN_REGS Registers
      3. 10.16.3 SSU_CPU1_CFG_REGS Registers
      4. 10.16.4 SSU_CPU2_CFG_REGS Registers
      5. 10.16.5 SSU_CPU3_CFG_REGS Registers
      6. 10.16.6 SSU_CPU1_AP_REGS Registers
      7. 10.16.7 SSU_CPU2_AP_REGS Registers
      8. 10.16.8 SSU_CPU3_AP_REGS Registers
  13. 11Configurable Logic Block (CLB)
    1. 11.1  Introduction
      1. 11.1.1 CLB Related Collateral
    2. 11.2  Description
      1. 11.2.1 CLB Clock
    3. 11.3  CLB Input/Output Connection
      1. 11.3.1 Overview
      2. 11.3.2 CLB Input Selection
      3. 11.3.3 CLB Output Selection
      4. 11.3.4 CLB Output Signal Multiplexer
    4. 11.4  CLB Tile
      1. 11.4.1 Static Switch Block
      2. 11.4.2 Counter Block
        1. 11.4.2.1 Counter Description
        2. 11.4.2.2 Counter Operation
        3. 11.4.2.3 Serializer Mode
        4. 11.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 11.4.3 FSM Block
      4. 11.4.4 LUT4 Block
      5. 11.4.5 Output LUT Block
      6. 11.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 11.4.7 High Level Controller (HLC)
        1. 11.4.7.1 High Level Controller Events
        2. 11.4.7.2 High Level Controller Instructions
        3. 11.4.7.3 <Src> and <Dest>
        4. 11.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 11.5  CPU Interface
      1. 11.5.1 Register Description
      2. 11.5.2 Non-Memory Mapped Registers
    6. 11.6  RTDMA Access
    7. 11.7  CLB Data Export Through SPI RX Buffer
    8. 11.8  CLB Pipeline Mode
    9. 11.9  Software
      1. 11.9.1 CLB Registers to Driverlib Functions
      2. 11.9.2 CLB Examples
    10. 11.10 CLB Registers
      1. 11.10.1 CLB Base Address Table
      2. 11.10.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 11.10.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 11.10.4 CLB_DATA_EXCHANGE_REGS Registers
  14. 12Dual-Clock Comparator (DCC)
    1. 12.1 Introduction
      1. 12.1.1 Features
      2. 12.1.2 Block Diagram
    2. 12.2 Module Operation
      1. 12.2.1 Configuring DCC Counters
      2. 12.2.2 Single-Shot Measurement Mode
      3. 12.2.3 Continuous Monitoring Mode
      4. 12.2.4 Error Conditions
    3. 12.3 Interrupts
    4. 12.4 Software
      1. 12.4.1 DCC Registers to Driverlib Functions
      2. 12.4.2 DCC Examples
        1. 12.4.2.1 DCC Single shot Clock verification - SINGLE_CORE
        2. 12.4.2.2 DCC Single shot Clock measurement - SINGLE_CORE
        3. 12.4.2.3 DCC Continuous clock monitoring - SINGLE_CORE
    5. 12.5 DCC Registers
      1. 12.5.1 DCC Base Address Table
      2. 12.5.2 DCC_REGS Registers
  15. 13Real-Time Direct Memory Access (RTDMA)
    1. 13.1  Introduction
      1. 13.1.1 Features
      2. 13.1.2 RTDMA Related Collateral
      3. 13.1.3 Block Diagram
    2. 13.2  RTDMA Trigger Source Options
    3. 13.3  RTDMA Bus
    4. 13.4  Address Pointer and Transfer Control
    5. 13.5  Pipeline Timing and Throughput
    6. 13.6  Channel Priority
      1. 13.6.1 Round-Robin Mode
      2. 13.6.2 Software Configurable Priority of Channels
    7. 13.7  Overrun Detection Feature
    8. 13.8  Burst Mode
    9. 13.9  Safety and Security
      1. 13.9.1 Safety
        1. 13.9.1.1 Lockstep Mode
        2. 13.9.1.2 Memory Protection Unit (MPU)
          1. 13.9.1.2.1 MPU Errors
      2. 13.9.2 Security
      3. 13.9.3 RTDMA Errors
      4. 13.9.4 Self-Test and Diagnostics
    10. 13.10 Software
      1. 13.10.1 RTDMA Registers to Driverlib Functions
      2. 13.10.2 RTDMA Examples
        1. 13.10.2.1 RTDMA Academy Lab - SINGLE_CORE
        2. 13.10.2.2 RTDMA Transfer - SINGLE_CORE
        3. 13.10.2.3 RTDMA Transfer with MPU - SINGLE_CORE
    11. 13.11 RTDMA Registers
      1. 13.11.1 RTDMA Base Address Table
      2. 13.11.2 RTDMA_REGS Registers
      3. 13.11.3 RTDMA_DIAG_REGS Registers
      4. 13.11.4 RTDMA_SELFTEST_REGS Registers
      5. 13.11.5 RTDMA_MPU_REGS Registers
      6. 13.11.6 RTDMA_CH_REGS Registers
  16. 14External Memory Interface (EMIF)
    1. 14.1 Introduction
      1. 14.1.1 Purpose of the Peripheral
      2. 14.1.2 Features
        1. 14.1.2.1 Asynchronous Memory Support
        2. 14.1.2.2 Synchronous DRAM Memory Support
      3. 14.1.3 Functional Block Diagram
      4. 14.1.4 Configuring Device Pins
    2. 14.2 EMIF Module Architecture
      1. 14.2.1  EMIF Clock Control
      2. 14.2.2  EMIF Requests
      3. 14.2.3  EMIF Signal Descriptions
      4. 14.2.4  EMIF Signal Multiplexing Control
      5. 14.2.5  SDRAM Controller and Interface
        1. 14.2.5.1  SDRAM Commands
        2. 14.2.5.2  Interfacing to SDRAM
        3. 14.2.5.3  SDRAM Configuration Registers
        4. 14.2.5.4  SDRAM Auto-Initialization Sequence
        5. 14.2.5.5  SDRAM Configuration Procedure
        6. 14.2.5.6  EMIF Refresh Controller
          1. 14.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 14.2.5.7  Self-Refresh Mode
        8. 14.2.5.8  Power-Down Mode
        9. 14.2.5.9  SDRAM Read Operation
        10. 14.2.5.10 SDRAM Write Operations
        11. 14.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 14.2.6  Asynchronous Controller and Interface
        1. 14.2.6.1 Interfacing to Asynchronous Memory
        2. 14.2.6.2 Accessing Larger Asynchronous Memories
        3. 14.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 14.2.6.4 Read and Write Operations in Normal Mode
          1. 14.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 14.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 14.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 14.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 14.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 14.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 14.2.7  Data Bus Parking
      8. 14.2.8  Reset and Initialization Considerations
      9. 14.2.9  Interrupt Support
        1. 14.2.9.1 Interrupt Events
      10. 14.2.10 RTDMA Event Support
      11. 14.2.11 EMIF Signal Multiplexing
      12. 14.2.12 Memory Map
      13. 14.2.13 Priority and Arbitration
      14. 14.2.14 System Considerations
        1. 14.2.14.1 Asynchronous Request Times
      15. 14.2.15 Power Management
        1. 14.2.15.1 Power Management Using Self-Refresh Mode
        2. 14.2.15.2 Power Management Using Power Down Mode
      16. 14.2.16 Emulation Considerations
    3. 14.3 EMIF Subsystem (EMIFSS)
      1. 14.3.1 Burst Support
      2. 14.3.2 EMIFSS Performance Improvement
      3. 14.3.3 Buffer Module
        1. 14.3.3.1 CPU Write FIFO
      4. 14.3.4 Emulation Mode
    4. 14.4 Example Configuration
      1. 14.4.1 Hardware Interface
      2. 14.4.2 Software Configuration
        1. 14.4.2.1 Configuring the SDRAM Interface
          1. 14.4.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 14.4.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 14.4.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 14.4.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 14.4.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 14.4.2.2 Configuring the Flash Interface
          1. 14.4.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    5. 14.5 Software
      1. 14.5.1 EMIF Registers to Driverlib Functions
      2. 14.5.2 EMIF Examples
    6. 14.6 EMIF Registers
      1. 14.6.1 EMIF Base Address Table
      2. 14.6.2 EMIF_REGS Registers
  17. 15General-Purpose Input/Output (GPIO)
    1. 15.1  Introduction
      1. 15.1.1 GPIO Related Collateral
    2. 15.2  Configuration Overview
    3. 15.3  Digital Inputs on ADC Pins (AIOs)
    4. 15.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 15.5  Digital General-Purpose I/O Control
    6. 15.6  Input Qualification
      1. 15.6.1 No Synchronization (Asynchronous Input)
      2. 15.6.2 Synchronization to SYSCLKOUT Only
      3. 15.6.3 Qualification Using a Sampling Window
    7. 15.7  PMBUS and I2C Signals
    8. 15.8  GPIO and Peripheral Muxing
      1. 15.8.1 GPIO Muxing
      2. 15.8.2 Peripheral Muxing
    9. 15.9  Internal Pullup Configuration Requirements
    10. 15.10 Software
      1. 15.10.1 GPIO Registers to Driverlib Functions
      2. 15.10.2 GPIO Examples
        1. 15.10.2.1 Device GPIO Toggle - SINGLE_CORE
        2. 15.10.2.2 XINT/XBAR example - SINGLE_CORE
      3. 15.10.3 LED Examples
        1. 15.10.3.1 LED Blinky Example - MULTI_CORE
        2. 15.10.3.2 LED Blinky Example (CPU1,CPU3) - MULTI_CORE
        3. 15.10.3.3 LED Blinky example - SINGLE_CORE
        4. 15.10.3.4 LED Blinky Example (CPU1|CPU2|CPU3) - MULTI_CORE
        5. 15.10.3.5 LED Blinky Example (CPU2) - MULTI_CORE
        6. 15.10.3.6 LED Blinky Example (CPU3) - MULTI_CORE
    11. 15.11 GPIO Registers
      1. 15.11.1 GPIO Base Address Table
      2. 15.11.2 GPIO_CTRL_REGS Registers
      3. 15.11.3 GPIO_DATA_REGS Registers
      4. 15.11.4 GPIO_DATA_READ_REGS Registers
  18. 16Interprocessor Communication (IPC)
    1. 16.1 Introduction
    2. 16.2 IPC Flags and Interrupts
    3. 16.3 IPC Command Registers
    4. 16.4 Free-Running Counter
    5. 16.5 IPC Communication Protocol
    6. 16.6 Software
      1. 16.6.1 IPC Registers to Driverlib Functions
      2. 16.6.2 IPC Examples
        1. 16.6.2.1 IPC basic message passing example with interrupt - MULTI_CORE
        2. 16.6.2.2 IPC basic message passing example with interrupt - MULTI_CORE
        3. 16.6.2.3 IPC basic message passing example with interrupt - MULTI_CORE
        4. 16.6.2.4 IPC basic message passing example with interrupt - MULTI_CORE
    7. 16.7 IPC Registers
      1. 16.7.1 IPC Base Address Table
      2. 16.7.2 IPC_COUNTER_REGS Registers
      3. 16.7.3 CPU1_IPC_SEND_REGS Registers
      4. 16.7.4 CPU2_IPC_SEND_REGS Registers
      5. 16.7.5 CPU3_IPC_SEND_REGS Registers
      6. 16.7.6 CPU1_IPC_RCV_REGS Registers
      7. 16.7.7 CPU2_IPC_RCV_REGS Registers
      8. 16.7.8 CPU3_IPC_RCV_REGS Registers
  19. 17Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 17.1 Introduction
    2. 17.2 Enhanced Bus Comparator Unit
      1. 17.2.1 Enhanced Bus Comparator Unit Operations
      2. 17.2.2 Stack Qualification
      3. 17.2.3 Event Masking and Exporting
    3. 17.3 System Event Counter Unit
      1. 17.3.1 System Event Counter Modes
        1. 17.3.1.1 Counting Active Levels Versus Edges
        2. 17.3.1.2 Max and Min Mode
        3. 17.3.1.3 Cumulative Mode
        4. 17.3.1.4 Input Signal Selection
      2. 17.3.2 Reset on Event
      3. 17.3.3 Operation Conditions
    4. 17.4 Program Counter Trace
      1. 17.4.1 Functional Block Diagram
      2. 17.4.2 Trace Qualification Modes
        1. 17.4.2.1 Trace Input Signal Conditioning
      3. 17.4.3 Trace Memory
      4. 17.4.4 PC Trace Software Operation
      5. 17.4.5 Trace Operation in Debug Mode
    5. 17.5 ERAD Ownership, Initialization, and Reset
      1. 17.5.1 Feature Level Ownership
      2. 17.5.2 Feature Access Security Mechanism
      3. 17.5.3 PC Trace Access Security Mechanism
    6. 17.6 ERAD Programming Sequence
      1. 17.6.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 17.6.2 Timer and Counter Programming Sequence
    7. 17.7 Software
      1. 17.7.1 ERAD Registers to Driverlib Functions
    8. 17.8 ERAD Registers
      1. 17.8.1 ERAD Base Address Table
        1. 17.8.1.1 ERAD_REGS Registers
  20. 18Data Logger and Trace (DLT)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 DLT Related Collateral
      3. 18.1.3 Interfaces
        1. 18.1.3.1 Block Diagram
    2. 18.2 Functional Overview
      1. 18.2.1 DLT Configuration
        1. 18.2.1.1 LINK Filter
        2. 18.2.1.2 TAG Filter
        3. 18.2.1.3 ERAD Event Trigger
        4. 18.2.1.4 Concurrent FILTERING modes
      2. 18.2.2 Time-stamping
      3. 18.2.3 FIFO Construction
        1. 18.2.3.1 FIFO Interrupt
    3. 18.3 Software
      1. 18.3.1 DLT Registers to Driverlib Functions
      2. 18.3.2 DLT Examples
        1. 18.3.2.1 DLT TAG filter example - SINGLE_CORE
        2. 18.3.2.2 DLT TAG filter example - SINGLE_CORE
        3. 18.3.2.3 DLT ERAD filter example - SINGLE_CORE
    4. 18.4 DLT Registers
      1. 18.4.1 DLT Base Address Table
      2. 18.4.2 DLT_CORE_REGS Registers
      3. 18.4.3 DLT_FIFO_REGS Registers
  21. 19Waveform Analyzer Diagnostic (WADI)
    1. 19.1 WADI Overview
      1. 19.1.1 Features
      2. 19.1.2 WADI Related Collateral
      3. 19.1.3 Block Diagram
      4. 19.1.4 Description
    2. 19.2 Signal and Trigger Input Configuration
      1. 19.2.1 SIG1 and SIG2 Configuration
      2. 19.2.2 Trigger 1 and Trigger 2
    3. 19.3 WADI Block
      1. 19.3.1 Overview
      2. 19.3.2 Counters
      3. 19.3.3 Pulse Width
        1. 19.3.3.1 Pulse Width Single Measurement
        2. 19.3.3.2 Pulse Width Aggregation
        3. 19.3.3.3 Pulse Width Average and Peak
      4. 19.3.4 Edge Count
        1. 19.3.4.1 Edge Count with Fixed Window
        2. 19.3.4.2 Edge Count with Moving Window
      5. 19.3.5 Signal1 to Signal2 Comparison
      6. 19.3.6 Dead Band and Phase
      7. 19.3.7 Simultaneous Measurement
    4. 19.4 Safe State Sequencer (SSS)
      1. 19.4.1 SSS Configuration
    5. 19.5 Lock and Commit Registers
    6. 19.6 Interrupt and Error Handling
    7. 19.7 RTDMA Interfaces
      1. 19.7.1 RTDMA Trigger
    8. 19.8 Software
      1. 19.8.1 WADI Registers to Driverlib Functions
      2. 19.8.2 WADI Examples
        1. 19.8.2.1 WADI Duty and Frequency check - SINGLE_CORE
    9. 19.9 WADI Registers
      1. 19.9.1 WADI Base Address Table
      2. 19.9.2 WADI_CONFIG_REGS Registers
      3. 19.9.3 WADI_OPER_SSS_REGS Registers
  22. 20Crossbar (X-BAR)
    1. 20.1 X-BAR Related Collateral
    2. 20.2 Input X-BAR, ICL XBAR, MINDB XBAR,
      1. 20.2.1 ICL and MINDB X-BAR
    3. 20.3 ePWM , CLB, and GPIO Output X-BAR
      1. 20.3.1 ePWM X-BAR
        1. 20.3.1.1 ePWM X-BAR Architecture
      2. 20.3.2 CLB X-BAR
        1. 20.3.2.1 CLB X-BAR Architecture
      3. 20.3.3 GPIO Output X-BAR
        1. 20.3.3.1 GPIO Output X-BAR Architecture
      4. 20.3.4 X-BAR Flags
    4. 20.4 Software
      1. 20.4.1 INPUT_XBAR Registers to Driverlib Functions
      2. 20.4.2 EPWM_XBAR Registers to Driverlib Functions
      3. 20.4.3 CLB_XBAR Registers to Driverlib Functions
      4. 20.4.4 OUTPUT_XBAR Registers to Driverlib Functions
      5. 20.4.5 MDL_XBAR Registers to Driverlib Functions
      6. 20.4.6 ICL_XBAR Registers to Driverlib Functions
      7. 20.4.7 XBAR Registers to Driverlib Functions
      8. 20.4.8 XBAR Examples
        1. 20.4.8.1 Input XBAR to Output XBAR Connection - SINGLE_CORE
        2. 20.4.8.2 Output XBAR Pulse Stretch - SINGLE_CORE
    5. 20.5 XBAR Registers
      1. 20.5.1 XBAR Base Address Table
      2. 20.5.2 INPUT_XBAR_REGS Registers
      3. 20.5.3 EPWM_XBAR_REGS Registers
      4. 20.5.4 CLB_XBAR_REGS Registers
      5. 20.5.5 OUTPUTXBAR_REGS Registers
      6. 20.5.6 MDL_XBAR_REGS Registers
      7. 20.5.7 ICL_XBAR_REGS Registers
      8. 20.5.8 OUTPUTXBAR_FLAG_REGS Registers
      9. 20.5.9 XBAR_REGS Registers
  23. 21Embedded Pattern Generator (EPG)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 EPG Block Diagram
      3. 21.1.3 EPG Related Collateral
    2. 21.2 Clock Generator Modules
      1. 21.2.1 DCLK (50% duty cycle clock)
      2. 21.2.2 Clock Stop
    3. 21.3 Signal Generator Module
    4. 21.4 EPG Peripheral Signal Mux Selection
    5. 21.5 Application Software Notes
    6. 21.6 EPG Example Use Cases
      1. 21.6.1 EPG Example: Synchronous Clocks with Offset
        1. 21.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 21.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 21.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 21.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 21.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
      4. 21.6.4 EPG Example: Clock and Data Pair
        1. 21.6.4.1 Clock and Data Pair Register Configuration
      5. 21.6.5 EPG Example: Clock and Skewed Data Pair
        1. 21.6.5.1 Clock and Skewed Data Pair Register Configuration
      6. 21.6.6 EPG Example: Capturing Serial Data with a Known Baud Rate
        1. 21.6.6.1 Capturing Serial Data with a Known Baud Rate Register Configuration
    7. 21.7 EPG Interrupt
    8. 21.8 Software
      1. 21.8.1 EPG Registers to Driverlib Functions
      2. 21.8.2 EPG Examples
        1. 21.8.2.1 EPG Generating Synchronous Clocks - SINGLE_CORE
        2. 21.8.2.2 EPG Generating Two Offset Clocks - SINGLE_CORE
        3. 21.8.2.3 EPG Generating Two Offset Clocks With SIGGEN - SINGLE_CORE
        4. 21.8.2.4 EPG Generate Serial Data - SINGLE_CORE
        5. 21.8.2.5 EPG Generate Serial Data Shift Mode - SINGLE_CORE
    9. 21.9 EPG Registers
      1. 21.9.1 EPG Base Address Table
      2. 21.9.2 EPG_REGS Registers
      3. 21.9.3 EPG_MUX_REGS Registers
  24. 22â–º ANALOG PERIPHERALS
    1.     Technical Reference Manual Overview
  25. 23Analog Subsystem
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 Block Diagram
    2. 23.2 Optimizing Power-Up Time
    3. 23.3 Digital Inputs on ADC Pins (AIOs)
    4. 23.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 23.5 Analog Pins and Internal Connections
    6. 23.6 Software
      1. 23.6.1 ASYSCTL Registers to Driverlib Functions
    7. 23.7 Lock Registers
    8. 23.8 ASBSYS Registers
      1. 23.8.1 ASBSYS Base Address Table
      2. 23.8.2 ANALOG_SUBSYS_REGS Registers
  26. 24Analog-to-Digital Converter (ADC)
    1. 24.1  Introduction
      1. 24.1.1 ADC Related Collateral
      2. 24.1.2 Features
      3. 24.1.3 Block Diagram
    2. 24.2  ADC Configurability
      1. 24.2.1 Clock Configuration
      2. 24.2.2 Resolution
      3. 24.2.3 Voltage Reference
        1. 24.2.3.1 External Reference Mode
        2. 24.2.3.2 Internal Reference Mode
        3. 24.2.3.3 Ganged References
        4. 24.2.3.4 Selecting Reference Mode
      4. 24.2.4 Signal Mode
      5. 24.2.5 Expected Conversion Results
      6. 24.2.6 Interpreting Conversion Results
    3. 24.3  SOC Principle of Operation
      1. 24.3.1 SOC Configuration
      2. 24.3.2 Trigger Operation
        1. 24.3.2.1 Global Software Trigger
        2. 24.3.2.2 Trigger Repeaters
          1. 24.3.2.2.1 Oversampling Mode
          2. 24.3.2.2.2 Undersampling Mode
          3. 24.3.2.2.3 Trigger Phase Delay
          4. 24.3.2.2.4 Re-trigger Spread
          5. 24.3.2.2.5 Trigger Repeater Configuration
            1. 24.3.2.2.5.1 Register Shadow Updates
          6. 24.3.2.2.6 Re-Trigger Logic
          7. 24.3.2.2.7 Multi-Path Triggering Behavior
      3. 24.3.3 ADC Acquisition (Sample and Hold) Window
      4. 24.3.4 ADC Input Models
      5. 24.3.5 Channel Selection
        1. 24.3.5.1 External Channel Selection
          1. 24.3.5.1.1 External Channel Selection Timing
    4. 24.4  SOC Configuration Examples
      1. 24.4.1 Single Conversion from ePWM Trigger
      2. 24.4.2 Oversampled Conversion from ePWM Trigger
      3. 24.4.3 Multiple Conversions from CPU Timer Trigger
      4. 24.4.4 Software Triggering of SOCs
    5. 24.5  ADC Conversion Priority
    6. 24.6  Burst Mode
      1. 24.6.1 Burst Mode Example
      2. 24.6.2 Burst Mode Priority Example
    7. 24.7  EOC and Interrupt Operation
      1. 24.7.1 Interrupt Overflow
      2. 24.7.2 Continue to Interrupt Mode
      3. 24.7.3 Early Interrupt Configuration Mode
    8. 24.8  Post-Processing Blocks
      1. 24.8.1 PPB Offset Correction
      2. 24.8.2 PPB Error Calculation
      3. 24.8.3 PPB Result Delta Calculation
      4. 24.8.4 PPB Limit Detection and Zero-Crossing Detection
        1. 24.8.4.1 PPB Digital Trip Filter
      5. 24.8.5 PPB Sample Delay Capture
      6. 24.8.6 PPB Oversampling
        1. 24.8.6.1 Accumulation, Minimum, Maximum, and Average Functions
        2. 24.8.6.2 Outlier Rejection
    9. 24.9  Result Safety Checker
      1. 24.9.1 Result Safety Checker Operation
      2. 24.9.2 Result Safety Checker Interrupts and Events
    10. 24.10 Opens/Shorts Detection Circuit (OSDETECT)
      1. 24.10.1 Implementation
      2. 24.10.2 Detecting an Open Input Pin
      3. 24.10.3 Detecting a Shorted Input Pin
    11. 24.11 Power-Up Sequence
    12. 24.12 ADC Calibration
      1. 24.12.1 ADC Zero Offset Calibration
    13. 24.13 ADC Timings
      1. 24.13.1 ADC Timing Diagrams
      2. 24.13.2 Post-Processing Block Timings
    14. 24.14 Additional Information
      1. 24.14.1 Ensuring Synchronous Operation
        1. 24.14.1.1 Basic Synchronous Operation
        2. 24.14.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 24.14.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 24.14.1.4 Synchronous Operation with Different Resolutions
        5. 24.14.1.5 Non-overlapping Conversions
      2. 24.14.2 Choosing an Acquisition Window Duration
      3. 24.14.3 Achieving Simultaneous Sampling
      4. 24.14.4 Result Register Mapping
      5. 24.14.5 Internal Temperature Sensor
      6. 24.14.6 Designing an External Reference Circuit
      7. 24.14.7 Internal Test Mode
      8. 24.14.8 ADC Gain and Offset Calibration
    15. 24.15 Software
      1. 24.15.1 ADC Registers to Driverlib Functions
      2. 24.15.2 ADC Examples
        1. 24.15.2.1  ADC Software Triggering - SINGLE_CORE
        2. 24.15.2.2  ADC ePWM Triggering - SINGLE_CORE
        3. 24.15.2.3  ADC Temperature Sensor Conversion - SINGLE_CORE
        4. 24.15.2.4  ADC Synchronous SOC Software Force (adc_soc_software_sync) - SINGLE_CORE
        5. 24.15.2.5  ADC Continuous Triggering (adc_soc_continuous) - SINGLE_CORE
        6. 24.15.2.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma) - SINGLE_CORE
        7. 24.15.2.7  ADC PPB Offset (adc_ppb_offset) - SINGLE_CORE
        8. 24.15.2.8  ADC PPB Limits (adc_ppb_limits) - SINGLE_CORE
        9. 24.15.2.9  ADC PPB Delay Capture (adc_ppb_delay) - SINGLE_CORE
        10. 24.15.2.10 ADC ePWM Triggering Multiple SOC - SINGLE_CORE
        11. 24.15.2.11 ADC Burst Mode - SINGLE_CORE
        12. 24.15.2.12 ADC Burst Mode Oversampling - SINGLE_CORE
        13. 24.15.2.13 ADC SOC Oversampling - SINGLE_CORE
        14. 24.15.2.14 ADC PPB PWM trip (adc_ppb_pwm_trip) - SINGLE_CORE
        15. 24.15.2.15 ADC Trigger Repeater Oversampling - SINGLE_CORE
        16. 24.15.2.16 ADC Trigger Repeater Undersampling - SINGLE_CORE
        17. 24.15.2.17 ADC Safety Checker - SINGLE_CORE
    16. 24.16 ADC Registers
      1. 24.16.1 ADC Base Address Table
      2. 24.16.2 ADC_RESULT_REGS Registers
      3. 24.16.3 ADC_REGS Registers
      4. 24.16.4 ADC_SAFECHECK_REGS Registers
      5. 24.16.5 ADC_SAFECHECK_INTEVT_REGS Registers
      6. 24.16.6 ADC_GLOBAL_REGS Registers
  27. 25Buffered Digital-to-Analog Converter (DAC)
    1. 25.1 Introduction
      1. 25.1.1 DAC Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
    2. 25.2 Using the DAC
      1. 25.2.1 Initialization Sequence
      2. 25.2.2 DAC Offset Adjustment
      3. 25.2.3 EPWMSYNCPER Signal
    3. 25.3 Lock Registers
    4. 25.4 Software
      1. 25.4.1 DAC Registers to Driverlib Functions
      2. 25.4.2 DAC Examples
        1. 25.4.2.1 Buffered DAC Enable - SINGLE_CORE
        2. 25.4.2.2 Buffered DAC Random - SINGLE_CORE
    5. 25.5 DAC Registers
      1. 25.5.1 DAC Base Address Table
      2. 25.5.2 DAC_REGS Registers
  28. 26Comparator Subsystem (CMPSS)
    1. 26.1 Introduction
      1. 26.1.1 CMPSS Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Block Diagram
    2. 26.2 Comparator
    3. 26.3 Reference DAC
    4. 26.4 Ramp Generator
      1. 26.4.1 Ramp Generator Overview
      2. 26.4.2 Ramp Generator Behavior
      3. 26.4.3 Ramp Generator Behavior at Corner Cases
    5. 26.5 Digital Filter
      1. 26.5.1 Filter Initialization Sequence
    6. 26.6 Using the CMPSS
      1. 26.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 26.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 26.6.3 Calibrating the CMPSS
      4. 26.6.4 Enabling and Disabling the CMPSS Clock
    7. 26.7 Software
      1. 26.7.1 CMPSS Registers to Driverlib Functions
      2. 26.7.2 CMPSS Examples
        1. 26.7.2.1 CMPSS Asynchronous Trip - SINGLE_CORE
        2. 26.7.2.2 CMPSS Digital Filter Configuration - SINGLE_CORE
    8. 26.8 CMPSS Registers
      1. 26.8.1 CMPSS Base Address Table
      2. 26.8.2 CMPSS_REGS Registers
  29. 27â–º CONTROL PERIPHERALS
    1.     Technical Reference Manual Overview
  30. 28Enhanced Capture (eCAP)
    1. 28.1 Introduction
      1. 28.1.1 Features
      2. 28.1.2 ECAP Related Collateral
    2. 28.2 Description
    3. 28.3 Configuring Device Pins for the eCAP
    4. 28.4 Capture and APWM Operating Mode
    5. 28.5 Capture Mode Description
      1. 28.5.1  Event Prescaler
      2. 28.5.2  Glitch Filter
      3. 28.5.3  Edge Polarity Select and Qualifier
      4. 28.5.4  Continuous/One-Shot Control
      5. 28.5.5  32-Bit Counter and Phase Control
      6. 28.5.6  CAP1-CAP4 Registers
      7. 28.5.7  eCAP Synchronization
        1. 28.5.7.1 Example 1 - Using SWSYNC with ECAP Module
      8. 28.5.8  Interrupt Control
      9. 28.5.9  RTDMA Interrupt
      10. 28.5.10 ADC SOC Event
      11. 28.5.11 Shadow Load and Lockout Control
      12. 28.5.12 APWM Mode Operation
      13. 28.5.13 Signal Monitoring Unit
        1. 28.5.13.1 Pulse Width and Period Monitoring
        2. 28.5.13.2 Edge Monitoring
    6. 28.6 Application of the eCAP Module
      1. 28.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 28.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 28.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 28.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 28.7 Application of the APWM Mode
      1. 28.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 28.8 Software
      1. 28.8.1 ECAP Registers to Driverlib Functions
      2. 28.8.2 ECAP Examples
        1. 28.8.2.1 eCAP APWM Example - SINGLE_CORE
        2. 28.8.2.2 eCAP Capture PWM Example - SINGLE_CORE
        3. 28.8.2.3 eCAP APWM Phase-shift Example - SINGLE_CORE
    9. 28.9 ECAP Registers
      1. 28.9.1 ECAP Base Address Table
      2. 28.9.2 ECAP_REGS Registers
      3. 28.9.3 ECAP_SIGNAL_MONITORING Registers
      4. 28.9.4 HRCAP_REGS Registers
  31. 29High Resolution Capture (HRCAP)
    1. 29.1 Introduction
      1. 29.1.1 HRCAP Related Collateral
      2. 29.1.2 Features
      3. 29.1.3 Description
    2. 29.2 Operational Details
      1. 29.2.1 HRCAP Clocking
      2. 29.2.2 HRCAP Initialization Sequence
      3. 29.2.3 HRCAP Interrupts
      4. 29.2.4 HRCAP Calibration
        1. 29.2.4.1 Applying the Scale Factor
    3. 29.3 Known Exceptions
    4. 29.4 Software
      1. 29.4.1 HRCAP Examples
        1. 29.4.1.1 HRCAP Capture and Calibration Example - SINGLE_CORE
    5. 29.5 HRCAP Registers
      1. 29.5.1 HRCAP Base Address Table
      2. 29.5.2 HRCAP_REGS Registers
  32. 30Enhanced Pulse Width Modulator (ePWM)
    1. 30.1  Introduction
      1. 30.1.1 EPWM Related Collateral
      2. 30.1.2 Submodule Overview
    2. 30.2  Configuring Device Pins
    3. 30.3  ePWM Modules Overview
    4. 30.4  Time-Base (TB) Submodule
      1. 30.4.1 Purpose of the Time-Base Submodule
      2. 30.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 30.4.3 Calculating PWM Period and Frequency
        1. 30.4.3.1 Time-Base Period Shadow Register
        2. 30.4.3.2 Time-Base Clock Synchronization
        3. 30.4.3.3 Time-Base Counter Synchronization
        4. 30.4.3.4 ePWM SYNC Selection
      4. 30.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 30.4.5 Simultaneous Writes Between ePWM Register Instances
      6. 30.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 30.4.7 Global Load
        1. 30.4.7.1 Global Load Pulse Pre-Scalar
        2. 30.4.7.2 One-Shot Load Mode
        3. 30.4.7.3 One-Shot Sync Mode
    5. 30.5  Counter-Compare (CC) Submodule
      1. 30.5.1 Purpose of the Counter-Compare Submodule
      2. 30.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 30.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 30.5.4 Count Mode Timing Waveforms
    6. 30.6  Action-Qualifier (AQ) Submodule
      1. 30.6.1 Purpose of the Action-Qualifier Submodule
      2. 30.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 30.6.3 Action-Qualifier Event Priority
      4. 30.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 30.6.5 Configuration Requirements for Common Waveforms
    7. 30.7  XCMP Complex Waveform Generator Mode
      1. 30.7.1 XCMP Allocation to CMPA and CMPB
      2. 30.7.2 XCMP Shadow Buffers
      3. 30.7.3 XCMP Operation
    8. 30.8  Dead-Band Generator (DB) Submodule
      1. 30.8.1 Purpose of the Dead-Band Submodule
      2. 30.8.2 Dead-band Submodule Additional Operating Modes
      3. 30.8.3 Operational Highlights for the Dead-Band Submodule
    9. 30.9  PWM Chopper (PC) Submodule
      1. 30.9.1 Purpose of the PWM Chopper Submodule
      2. 30.9.2 Operational Highlights for the PWM Chopper Submodule
      3. 30.9.3 Waveforms
        1. 30.9.3.1 One-Shot Pulse
        2. 30.9.3.2 Duty Cycle Control
    10. 30.10 Trip-Zone (TZ) Submodule
      1. 30.10.1 Purpose of the Trip-Zone Submodule
      2. 30.10.2 Operational Highlights for the Trip-Zone Submodule
        1. 30.10.2.1 Trip-Zone Configurations
      3. 30.10.3 Generating Trip Event Interrupts
    11. 30.11 Diode Emulation (DE) Submodule
      1. 30.11.1 DEACTIVE Mode
      2. 30.11.2 Exiting DE Mode
      3. 30.11.3 Re-Entering DE Mode
      4. 30.11.4 DE Monitor
    12. 30.12 Minimum Dead-Band (MINDB) + Illegal Combination Logic (ICL) Submodules
      1. 30.12.1 Minimum Dead-Band (MINDB)
      2. 30.12.2 Illegal Combo Logic (ICL)
    13. 30.13 Event-Trigger (ET) Submodule
      1. 30.13.1 Operational Overview of the ePWM Event-Trigger Submodule
    14. 30.14 Digital Compare (DC) Submodule
      1. 30.14.1 Purpose of the Digital Compare Submodule
      2. 30.14.2 Enhanced Trip Action Using CMPSS
      3. 30.14.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 30.14.4 Operation Highlights of the Digital Compare Submodule
        1. 30.14.4.1 Digital Compare Events
        2. 30.14.4.2 Event Filtering
        3. 30.14.4.3 Valley Switching
        4. 30.14.4.4 Event Detection
          1. 30.14.4.4.1 Input Signal Detection
          2. 30.14.4.4.2 MIN and MAX Detection Circuit
    15. 30.15 ePWM Crossbar (X-BAR)
    16. 30.16 Applications to Power Topologies
      1. 30.16.1  Overview of Multiple Modules
      2. 30.16.2  Key Configuration Capabilities
      3. 30.16.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 30.16.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 30.16.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 30.16.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 30.16.7  Practical Applications Using Phase Control Between PWM Modules
      8. 30.16.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 30.16.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 30.16.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 30.16.11 Controlling H-Bridge LLC Resonant Converter
    17. 30.17 Register Lock Protection
    18. 30.18 High-Resolution Pulse Width Modulator (HRPWM)
      1. 30.18.1 Operational Description of HRPWM
        1. 30.18.1.1 Controlling the HRPWM Capabilities
        2. 30.18.1.2 HRPWM Source Clock
        3. 30.18.1.3 Configuring the HRPWM
        4. 30.18.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 30.18.1.5 Principle of Operation
          1. 30.18.1.5.1 Edge Positioning
          2. 30.18.1.5.2 Scaling Considerations
          3. 30.18.1.5.3 Duty Cycle Range Limitation
          4. 30.18.1.5.4 High-Resolution Period
            1. 30.18.1.5.4.1 High-Resolution Period Configuration
        6. 30.18.1.6 Deadband High-Resolution Operation
        7. 30.18.1.7 Scale Factor Optimizing Software (SFO)
        8. 30.18.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 30.18.1.8.1 #Defines for HRPWM Header Files
          2. 30.18.1.8.2 Implementing a Simple Buck Converter
            1. 30.18.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 30.18.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 30.18.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 30.18.1.8.3.1 PWM DAC Function Initialization Code
            2. 30.18.1.8.3.2 PWM DAC Function Run-Time Code
      2. 30.18.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 30.18.2.1 Scale Factor Optimizer Function - int SFO()
        2. 30.18.2.2 Software Usage
          1. 30.18.2.2.1 A Sample of How to Add "Include" Files
          2.        1131
          3. 30.18.2.2.2 Declaring an Element
          4.        1133
          5. 30.18.2.2.3 Initializing With a Scale Factor Value
          6.        1135
          7. 30.18.2.2.4 SFO Function Calls
    19. 30.19 Software
      1. 30.19.1 EPWM Registers to Driverlib Functions
      2. 30.19.2 HRPWMCAL Registers to Driverlib Functions
      3. 30.19.3 EPWM Examples
        1. 30.19.3.1  ePWM Trip Zone - SINGLE_CORE
        2. 30.19.3.2  ePWM Up Down Count Action Qualifier - SINGLE_CORE
        3. 30.19.3.3  ePWM Synchronization - SINGLE_CORE
        4. 30.19.3.4  ePWM Digital Compare - SINGLE_CORE
        5. 30.19.3.5  ePWM Digital Compare Event Filter Blanking Window - SINGLE_CORE
        6. 30.19.3.6  ePWM Valley Switching - SINGLE_CORE
        7. 30.19.3.7  ePWM Digital Compare Edge Filter - SINGLE_CORE
        8. 30.19.3.8  ePWM Deadband - SINGLE_CORE
        9. 30.19.3.9  ePWM DMA - SINGLE_CORE
        10. 30.19.3.10 ePWM Chopper - SINGLE_CORE
        11. 30.19.3.11 EPWM Configure Signal - SINGLE_CORE
        12. 30.19.3.12 Realization of Monoshot mode - SINGLE_CORE
        13. 30.19.3.13 EPWM Action Qualifier (epwm_up_aq) - SINGLE_CORE
        14. 30.19.3.14 ePWM XCMP Mode - SINGLE_CORE
        15. 30.19.3.15 ePWM Event Detection - SINGLE_CORE
    20. 30.20 EPWM Registers
      1. 30.20.1 EPWM Base Address Table
      2. 30.20.2 EPWM_REGS Registers
      3. 30.20.3 EPWM_XCMP_REGS Registers
      4. 30.20.4 DE_REGS Registers
      5. 30.20.5 MINDB_LUT_REGS Registers
      6. 30.20.6 HRPWMCAL_REGS Registers
  33. 31Enhanced Quadrature Encoder Pulse (eQEP)
    1. 31.1  Introduction
      1. 31.1.1 EQEP Related Collateral
    2. 31.2  Configuring Device Pins
    3. 31.3  Description
      1. 31.3.1 EQEP Inputs
      2. 31.3.2 Functional Description
      3. 31.3.3 eQEP Memory Map
    4. 31.4  Quadrature Decoder Unit (QDU)
      1. 31.4.1 Position Counter Input Modes
        1. 31.4.1.1 Quadrature Count Mode
        2. 31.4.1.2 Direction-Count Mode
        3. 31.4.1.3 Up-Count Mode
        4. 31.4.1.4 Down-Count Mode
      2. 31.4.2 eQEP Input Polarity Selection
      3. 31.4.3 Position-Compare Sync Output
    5. 31.5  Position Counter and Control Unit (PCCU)
      1. 31.5.1 Position Counter Operating Modes
        1. 31.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM] = 00)
        2. 31.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM] = 01)
        3. 31.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 31.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 31.5.2 Position Counter Latch
        1. 31.5.2.1 Index Event Latch
        2. 31.5.2.2 Strobe Event Latch
      3. 31.5.3 Position Counter Initialization
      4. 31.5.4 eQEP Position-compare Unit
    6. 31.6  eQEP Edge Capture Unit
    7. 31.7  eQEP Watchdog
    8. 31.8  eQEP Unit Timer Base
    9. 31.9  QMA Module
      1. 31.9.1 Modes of Operation
        1. 31.9.1.1 QMA Mode-1 (QMACTRL[MODE] = 1)
        2. 31.9.1.2 QMA Mode-2 (QMACTRL[MODE] = 2)
      2. 31.9.2 Interrupt and Error Generation
    10. 31.10 eQEP Interrupt Structure
    11. 31.11 Software
      1. 31.11.1 EQEP Registers to Driverlib Functions
      2. 31.11.2 EQEP Examples
        1. 31.11.2.1 Frequency Measurement Using eQEP via unit timeout interrupt - SINGLE_CORE
        2. 31.11.2.2 Motor speed and direction measurement using eQEP via unit timeout interrupt - SINGLE_CORE
    12. 31.12 EQEP Registers
      1. 31.12.1 EQEP Base Address Table
      2. 31.12.2 EQEP_REGS Registers
  34. 32Sigma Delta Filter Module (SDFM)
    1. 32.1  Introduction
      1. 32.1.1 SDFM Related Collateral
      2. 32.1.2 Features
      3. 32.1.3 Block Diagram
    2. 32.2  Configuring Device Pins
    3. 32.3  Input Qualification
    4. 32.4  Input Control Unit
    5. 32.5  SDFM Clock Control
    6. 32.6  Sinc Filter
      1. 32.6.1 Data Rate and Latency of the Sinc Filter
    7. 32.7  Data (Primary) Filter Unit
      1. 32.7.1 32-bit or 16-bit Data Filter Output Representation
      2. 32.7.2 Data FIFO
      3. 32.7.3 SDSYNC Event
    8. 32.8  Comparator (Secondary) Filter Unit
      1. 32.8.1 Higher Threshold (HLT) Comparators
      2. 32.8.2 Lower Threshold (LLT) Comparators
      3. 32.8.3 Digital Filter
    9. 32.9  Theoretical SDFM Filter Output
    10. 32.10 Interrupt Unit
      1. 32.10.1 SDFM (SDyERR) Interrupt Sources
      2. 32.10.2 Data Ready (DRINT) Interrupt Sources
    11. 32.11 Software
      1. 32.11.1 SDFM Registers to Driverlib Functions
      2. 32.11.2 SDFM Examples
    12. 32.12 SDFM Registers
      1. 32.12.1 SDFM Base Address Table
      2. 32.12.2 SDFM_REGS Registers
  35. 33â–º COMMUNICATION PERIPHERALS
    1.     Technical Reference Manual Overview
  36. 34Modular Controller Area Network (MCAN)
    1. 34.1 MCAN Introduction
      1. 34.1.1 MCAN Related Collateral
      2. 34.1.2 MCAN Features
    2. 34.2 MCAN Environment
    3. 34.3 CAN Network Basics
    4. 34.4 MCAN Integration
    5. 34.5 MCAN Functional Description
      1. 34.5.1  Module Clocking Requirements
      2. 34.5.2  Interrupt Requests
      3. 34.5.3  Operating Modes
        1. 34.5.3.1 Software Initialization
        2. 34.5.3.2 Normal Operation
        3. 34.5.3.3 CAN FD Operation
      4. 34.5.4  Transmitter Delay Compensation
        1. 34.5.4.1 Description
        2. 34.5.4.2 Transmitter Delay Compensation Measurement
      5. 34.5.5  Restricted Operation Mode
      6. 34.5.6  Bus Monitoring Mode
      7. 34.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 34.5.7.1 Frame Transmission in DAR Mode
      8. 34.5.8  Clock Stop Mode
        1. 34.5.8.1 Suspend Mode
        2. 34.5.8.2 Wakeup Request
      9. 34.5.9  Test Modes
        1. 34.5.9.1 External Loop Back Mode
        2. 34.5.9.2 Internal Loop Back Mode
      10. 34.5.10 Timestamp Generation
        1. 34.5.10.1 External Timestamp Counter
      11. 34.5.11 Timeout Counter
      12. 34.5.12 Safety
        1. 34.5.12.1 ECC Wrapper
        2. 34.5.12.2 ECC Aggregator
          1. 34.5.12.2.1 ECC Aggregator Overview
          2. 34.5.12.2.2 ECC Aggregator Registers
        3. 34.5.12.3 Reads to ECC Control and Status Registers
        4. 34.5.12.4 ECC Interrupts
      13. 34.5.13 Rx Handling
        1. 34.5.13.1 Acceptance Filtering
          1. 34.5.13.1.1 Range Filter
          2. 34.5.13.1.2 Filter for Specific IDs
          3. 34.5.13.1.3 Classic Bit Mask Filter
          4. 34.5.13.1.4 Standard Message ID Filtering
          5. 34.5.13.1.5 Extended Message ID Filtering
        2. 34.5.13.2 Rx FIFOs
          1. 34.5.13.2.1 Rx FIFO Blocking Mode
          2. 34.5.13.2.2 Rx FIFO Overwrite Mode
        3. 34.5.13.3 Dedicated Rx Buffers
          1. 34.5.13.3.1 Rx Buffer Handling
      14. 34.5.14 Tx Handling
        1. 34.5.14.1 Transmit Pause
        2. 34.5.14.2 Dedicated Tx Buffers
        3. 34.5.14.3 Tx FIFO
        4. 34.5.14.4 Tx Queue
        5. 34.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 34.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 34.5.14.7 Transmit Cancellation
        8. 34.5.14.8 Tx Event Handling
      15. 34.5.15 FIFO Acknowledge Handling
      16. 34.5.16 Message RAM
        1. 34.5.16.1 Message RAM Configuration
        2. 34.5.16.2 Rx Buffer and FIFO Element
        3. 34.5.16.3 Tx Buffer Element
        4. 34.5.16.4 Tx Event FIFO Element
        5. 34.5.16.5 Standard Message ID Filter Element
        6. 34.5.16.6 Extended Message ID Filter Element
    6. 34.6 Software
      1. 34.6.1 MCAN Examples
        1. 34.6.1.1 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
        2. 34.6.1.2 MCAN Loopback with Polling Example Using SYSCONFIG Tool - SINGLE_CORE
        3. 34.6.1.3 MCAN Loopback with Interrupts Example Using SYSCONFIG Tool - SINGLE_CORE
    7. 34.7 MCAN Registers
      1. 34.7.1 MCAN Base Address Table
      2. 34.7.2 MCANSS_REGS Registers
      3. 34.7.3 MCAN_REGS Registers
      4. 34.7.4 MCAN_ERROR_REGS Registers
  37. 35EtherCAT® SubordinateDevice Controller (ESC)
    1. 35.1 Introduction
      1. 35.1.1  EtherCAT Related Collateral
      2. 35.1.2  ESC Features
      3. 35.1.3  ESC Subsystem Integrated Features
      4. 35.1.4  ESC versus Beckhoff ET1100
      5. 35.1.5  EtherCAT IP Block Diagram
      6. 35.1.6  ESC Functional Blocks
        1. 35.1.6.1  Interface to EtherCAT MainDevice
        2. 35.1.6.2  Process Data Interface
        3. 35.1.6.3  General-Purpose Inputs and Outputs
        4. 35.1.6.4  EtherCAT Processing Unit (EPU)
        5. 35.1.6.5  Fieldbus Memory Management Unit (FMMU)
        6. 35.1.6.6  Sync Manager
        7. 35.1.6.7  Monitoring
        8. 35.1.6.8  Reset Controller
        9. 35.1.6.9  PHY Management
        10. 35.1.6.10 Distributed Clock (DC)
        11. 35.1.6.11 EEPROM
        12. 35.1.6.12 Status / LEDs
      7. 35.1.7  EtherCAT Physical Layer
        1. 35.1.7.1 MII Interface
        2. 35.1.7.2 PHY Management Interface
          1. 35.1.7.2.1 PHY Address Configuration
          2. 35.1.7.2.2 PHY Reset Signal
          3. 35.1.7.2.3 PHY Clock
      8. 35.1.8  EtherCAT Protocol
      9. 35.1.9  EtherCAT State Machine (ESM)
      10. 35.1.10 More Information on EtherCAT
      11. 35.1.11 Beckhoff® Automation EtherCAT IP Errata
    2. 35.2 ESC and ESCSS Description
      1. 35.2.1  ESC RAM Parity and Memory Address Maps
        1. 35.2.1.1 ESC RAM Parity Logic
        2. 35.2.1.2 CPU1 ESC Memory Address Map
        3. 35.2.1.3 CPU2 ESC Memory Address Map
      2. 35.2.2  Local Host Communication
        1. 35.2.2.1 Byte Accessibility Through PDI
        2. 35.2.2.2 Software Details for Operation Across Clock Domains
      3. 35.2.3  Debug Emulation Mode Operation
      4. 35.2.4  ESC SubSystem
        1. 35.2.4.1 CPU1 Bus Interface
        2. 35.2.4.2 CPU2/CPU3 Bus Interface
      5. 35.2.5  Interrupts and Interrupt Mapping
      6. 35.2.6  Power, Clocks, and Resets
        1. 35.2.6.1 Power
        2. 35.2.6.2 Clocking
        3. 35.2.6.3 Resets
          1. 35.2.6.3.1 Chip-Level Reset
          2. 35.2.6.3.2 EtherCAT Soft Resets
          3. 35.2.6.3.3 Reset Out (RESET_OUT)
      7. 35.2.7  LED Controls
      8. 35.2.8  SubordinateDevice Node Configuration and EEPROM
      9. 35.2.9  General-Purpose Inputs and Outputs
        1. 35.2.9.1 General-Purpose Inputs
        2. 35.2.9.2 General-Purpose Output
      10. 35.2.10 Distributed Clocks – Sync and Latch
        1. 35.2.10.1 Clock Synchronization
        2. 35.2.10.2 SYNC Signals
          1. 35.2.10.2.1 Seeking Host Intervention
        3. 35.2.10.3 LATCH Signals
          1. 35.2.10.3.1 Timestamping
        4. 35.2.10.4 Device Control and Synchronization
          1. 35.2.10.4.1 Synchronization of PWM
          2. 35.2.10.4.2 ECAP SYNC Inputs
          3. 35.2.10.4.3 SYNC Signal Conditioning and Rerouting
    3. 35.3 Software Initialization Sequence and Allocating Ownership
    4. 35.4 ESC Configuration Constants
    5. 35.5 Software
      1. 35.5.1 ECAT_SS Registers to Driverlib Functions
      2. 35.5.2 ETHERNET Examples
    6. 35.6 ETHERCAT Registers
      1. 35.6.1 ETHERCAT Base Address Table
      2. 35.6.2 ESCSS_REGS Registers
      3. 35.6.3 ESCSS_CONFIG_REGS Registers
  38. 36Fast Serial Interface (FSI)
    1. 36.1 Introduction
      1. 36.1.1 FSI Related Collateral
      2. 36.1.2 FSI Features
    2. 36.2 System-level Integration
      1. 36.2.1 CPU Interface
      2. 36.2.2 Signal Description
        1. 36.2.2.1 Configuring Device Pins
      3. 36.2.3 FSI Interrupts
        1. 36.2.3.1 Transmitter Interrupts
        2. 36.2.3.2 Receiver Interrupts
        3. 36.2.3.3 Configuring Interrupts
        4. 36.2.3.4 Handling Interrupts
      4. 36.2.4 RTDMA Interface
      5. 36.2.5 External Frame Trigger Mux
    3. 36.3 FSI Functional Description
      1. 36.3.1 Introduction to Operation
      2. 36.3.2 FSI Transmitter Module
        1. 36.3.2.1 Initialization
        2. 36.3.2.2 FSI_TX Clocking
        3. 36.3.2.3 Transmitting Frames
          1. 36.3.2.3.1 Software Triggered Frames
          2. 36.3.2.3.2 Externally Triggered Frames
          3. 36.3.2.3.3 Ping Frame Generation
            1. 36.3.2.3.3.1 Automatic Ping Frames
            2. 36.3.2.3.3.2 Software Triggered Ping Frame
            3. 36.3.2.3.3.3 Externally Triggered Ping Frame
          4. 36.3.2.3.4 Transmitting Frames with RTDMA
        4. 36.3.2.4 Transmit Buffer Management
        5. 36.3.2.5 CRC Submodule
        6. 36.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 36.3.2.7 Reset
      3. 36.3.3 FSI Receiver Module
        1. 36.3.3.1  Initialization
        2. 36.3.3.2  FSI_RX Clocking
        3. 36.3.3.3  Receiving Frames
          1. 36.3.3.3.1 Receiving Frames with RTDMA
        4. 36.3.3.4  Ping Frame Watchdog
        5. 36.3.3.5  Frame Watchdog
        6. 36.3.3.6  Delay Line Control
        7. 36.3.3.7  Buffer Management
        8. 36.3.3.8  CRC Submodule
        9. 36.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 36.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 36.3.3.11 FSI_RX Reset
      4. 36.3.4 Frame Format
        1. 36.3.4.1 FSI Frame Phases
        2. 36.3.4.2 Frame Types
          1. 36.3.4.2.1 Ping Frames
          2. 36.3.4.2.2 Error Frames
          3. 36.3.4.2.3 Data Frames
        3. 36.3.4.3 Multi-Lane Transmission
      5. 36.3.5 Flush Sequence
      6. 36.3.6 Internal Loopback
      7. 36.3.7 CRC Generation
      8. 36.3.8 ECC Module
      9. 36.3.9 FSI-SPI Compatibility Mode
        1. 36.3.9.1 Available SPI Modes
          1. 36.3.9.1.1 FSITX as SPI Controller, Transmit Only
            1. 36.3.9.1.1.1 Initialization
            2. 36.3.9.1.1.2 Operation
          2. 36.3.9.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 36.3.9.1.2.1 Initialization
            2. 36.3.9.1.2.2 Operation
          3. 36.3.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 36.3.9.1.3.1 Initialization
            2. 36.3.9.1.3.2 Operation
    4. 36.4 FSI Programing Guide
      1. 36.4.1 Establishing the Communication Link
        1. 36.4.1.1 Establishing the Communication Link from the Main Device
        2. 36.4.1.2 Establishing the Communication Link from the Remote Device
      2. 36.4.2 Register Protection
      3. 36.4.3 Emulation Mode
    5. 36.5 Software
      1. 36.5.1 FSI Registers to Driverlib Functions
      2. 36.5.2 FSI Examples
        1. 36.5.2.1 FSI Loopback:CPU Control - SINGLE_CORE
        2. 36.5.2.2 FSI data transfers upon CPU Timer event - SINGLE_CORE
    6. 36.6 FSI Registers
      1. 36.6.1 FSI Base Address Table
      2. 36.6.2 FSI_TX_REGS Registers
      3. 36.6.3 FSI_RX_REGS Registers
  39. 37Inter-Integrated Circuit Module (I2C)
    1. 37.1 Introduction
      1. 37.1.1 I2C Related Collateral
      2. 37.1.2 Features
      3. 37.1.3 Features Not Supported
      4. 37.1.4 Functional Overview
      5. 37.1.5 Clock Generation
      6. 37.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 37.1.6.1 Formula for the Controller Clock Period
    2. 37.2 Configuring Device Pins
    3. 37.3 I2C Module Operational Details
      1. 37.3.1  Input and Output Voltage Levels
      2. 37.3.2  Selecting Pullup Resistors
      3. 37.3.3  Data Validity
      4. 37.3.4  Operating Modes
      5. 37.3.5  I2C Module START and STOP Conditions
      6. 37.3.6  Non-repeat Mode versus Repeat Mode
      7. 37.3.7  Serial Data Formats
        1. 37.3.7.1 7-Bit Addressing Format
        2. 37.3.7.2 10-Bit Addressing Format
        3. 37.3.7.3 Free Data Format
        4. 37.3.7.4 Using a Repeated START Condition
      8. 37.3.8  Clock Synchronization
      9. 37.3.9  Clock Stretching
      10. 37.3.10 Arbitration
      11. 37.3.11 Digital Loopback Mode
      12. 37.3.12 NACK Bit Generation
    4. 37.4 Interrupt Requests Generated by the I2C Module
      1. 37.4.1 Basic I2C Interrupt Requests
      2. 37.4.2 I2C FIFO Interrupts
    5. 37.5 Resetting or Disabling the I2C Module
    6. 37.6 Software
      1. 37.6.1 I2C Registers to Driverlib Functions
      2. 37.6.2 I2C Examples
        1. 37.6.2.1 I2C Digital Loopback with FIFO Interrupts - SINGLE_CORE
        2. 37.6.2.2 I2C EEPROM - SINGLE_CORE
        3. 37.6.2.3 I2C Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        4. 37.6.2.4 I2C Extended Clock Stretching Controller TX - SINGLE_CORE
        5. 37.6.2.5 I2C Extended Clock Stretching Target RX - SINGLE_CORE
    7. 37.7 I2C Registers
      1. 37.7.1 I2C Base Address Table
      2. 37.7.2 I2C_REGS Registers
  40. 38Power Management Bus Module (PMBus)
    1. 38.1 Introduction
      1. 38.1.1 PMBUS Related Collateral
      2. 38.1.2 Features
      3. 38.1.3 Block Diagram
    2. 38.2 Configuring Device Pins
    3. 38.3 Target Mode Operation
      1. 38.3.1 Configuration
      2. 38.3.2 Message Handling
        1. 38.3.2.1  Quick Command
        2. 38.3.2.2  Send Byte
        3. 38.3.2.3  Receive Byte
        4. 38.3.2.4  Write Byte and Write Word
        5. 38.3.2.5  Read Byte and Read Word
        6. 38.3.2.6  Process Call
        7. 38.3.2.7  Block Write
        8. 38.3.2.8  Block Read
        9. 38.3.2.9  Block Write-Block Read Process Call
        10. 38.3.2.10 Alert Response
        11. 38.3.2.11 Extended Command
        12. 38.3.2.12 Group Command
    4. 38.4 Controller Mode Operation
      1. 38.4.1 Configuration
      2. 38.4.2 Message Handling
        1. 38.4.2.1  Quick Command
        2. 38.4.2.2  Send Byte
        3. 38.4.2.3  Receive Byte
        4. 38.4.2.4  Write Byte and Write Word
        5. 38.4.2.5  Read Byte and Read Word
        6. 38.4.2.6  Process Call
        7. 38.4.2.7  Block Write
        8. 38.4.2.8  Block Read
        9. 38.4.2.9  Block Write-Block Read Process Call
        10. 38.4.2.10 Alert Response
        11. 38.4.2.11 Extended Command
        12. 38.4.2.12 Group Command
    5. 38.5 Software
      1. 38.5.1 PMBUS Registers to Driverlib Functions
    6. 38.6 PMBUS Registers
      1. 38.6.1 PMBUS Base Address Table
      2. 38.6.2 PMBUS_REGS Registers
  41. 39Universal Asynchronous Receiver/Transmitter (UART)
    1. 39.1 Introduction
      1. 39.1.1 Features
      2. 39.1.2 UART Related Collateral
      3. 39.1.3 Block Diagram
    2. 39.2 Functional Description
      1. 39.2.1 Transmit and Receive Logic
      2. 39.2.2 Baud-Rate Generation
      3. 39.2.3 Data Transmission
      4. 39.2.4 Serial IR (SIR)
      5. 39.2.5 9-Bit UART Mode
      6. 39.2.6 FIFO Operation
      7. 39.2.7 Interrupts
      8. 39.2.8 Loopback Operation
      9. 39.2.9 RTDMA Operation
        1. 39.2.9.1 Receiving Data Using UART with RTDMA
        2. 39.2.9.2 Transmitting Data Using UART with RTDMA
    3. 39.3 Initialization and Configuration
    4. 39.4 Software
      1. 39.4.1 UART Registers to Driverlib Functions
      2. 39.4.2 UART Examples
        1. 39.4.2.1 UART Loopback - SINGLE_CORE
        2. 39.4.2.2 UART Loopback with Interrupt - SINGLE_CORE
        3. 39.4.2.3 UART Loopback with DMA - SINGLE_CORE
        4. 39.4.2.4 UART Echoback - SINGLE_CORE
    5. 39.5 UART Registers
      1. 39.5.1 UART Base Address Table
      2. 39.5.2 UART_REGS Registers
      3. 39.5.3 UART_REGS_WRITE Registers
  42. 40Local Interconnect Network (LIN)
    1. 40.1 LIN Overview
      1. 40.1.1 LIN Mode Features
      2. 40.1.2 SCI Mode Features
      3. 40.1.3 Block Diagram
    2. 40.2 Serial Communications Interface Module
      1. 40.2.1 SCI Communication Formats
        1. 40.2.1.1 SCI Frame Formats
        2. 40.2.1.2 SCI Asynchronous Timing Mode
        3. 40.2.1.3 SCI Baud Rate
          1. 40.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 40.2.1.4 SCI Multiprocessor Communication Modes
          1. 40.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 40.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 40.2.1.5 SCI Multibuffered Mode
      2. 40.2.2 SCI Interrupts
        1. 40.2.2.1 Transmit Interrupt
        2. 40.2.2.2 Receive Interrupt
        3. 40.2.2.3 WakeUp Interrupt
        4. 40.2.2.4 Error Interrupts
      3. 40.2.3 SCI RTDMA Interface
        1. 40.2.3.1 Receive RTDMA Requests
        2. 40.2.3.2 Transmit RTDMA Requests
      4. 40.2.4 SCI Configurations
        1. 40.2.4.1 Receiving Data
          1. 40.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 40.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 40.2.4.2 Transmitting Data
          1. 40.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 40.2.5 SCI Low-Power Mode
        1. 40.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 40.3 Local Interconnect Network Module
      1. 40.3.1 LIN Communication Formats
        1. 40.3.1.1  LIN Standards
        2. 40.3.1.2  Message Frame
          1. 40.3.1.2.1 Message Header
          2. 40.3.1.2.2 Response
        3. 40.3.1.3  Synchronizer
        4. 40.3.1.4  Baud Rate
          1. 40.3.1.4.1 Fractional Divider
          2. 40.3.1.4.2 Superfractional Divider
            1. 40.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 40.3.1.5  Header Generation
          1. 40.3.1.5.1 Event Triggered Frame Handling
          2. 40.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 40.3.1.6  Extended Frames Handling
        7. 40.3.1.7  Timeout Control
          1. 40.3.1.7.1 No-Response Error (NRE)
          2. 40.3.1.7.2 Bus Idle Detection
          3. 40.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 40.3.1.8  TXRX Error Detector (TED)
          1. 40.3.1.8.1 Bit Errors
          2. 40.3.1.8.2 Physical Bus Errors
          3. 40.3.1.8.3 ID Parity Errors
          4. 40.3.1.8.4 Checksum Errors
        9. 40.3.1.9  Message Filtering and Validation
        10. 40.3.1.10 Receive Buffers
        11. 40.3.1.11 Transmit Buffers
      2. 40.3.2 LIN Interrupts
      3. 40.3.3 Servicing LIN Interrupts
      4. 40.3.4 LIN RTDMA Interface
        1. 40.3.4.1 LIN Receive RTDMA Requests
        2. 40.3.4.2 LIN Transmit RTDMA Requests
      5. 40.3.5 LIN Configurations
        1. 40.3.5.1 Receiving Data
          1. 40.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 40.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 40.3.5.2 Transmitting Data
          1. 40.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 40.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 40.4 Low-Power Mode
      1. 40.4.1 Entering Sleep Mode
      2. 40.4.2 Wakeup
      3. 40.4.3 Wakeup Timeouts
    5. 40.5 Emulation Mode
    6. 40.6 Software
      1. 40.6.1 LIN Registers to Driverlib Functions
      2. 40.6.2 LIN Examples
        1. 40.6.2.1 LIN Internal Loopback with Interrupts - SINGLE_CORE
        2. 40.6.2.2 LIN SCI Mode Internal Loopback with Interrupts - SINGLE_CORE
        3. 40.6.2.3 LIN SCI MODE Internal Loopback with DMA - SINGLE_CORE
        4. 40.6.2.4 LIN Internal Loopback without interrupts (polled mode) - SINGLE_CORE
        5. 40.6.2.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA - SINGLE_CORE
    7. 40.7 LIN Registers
      1. 40.7.1 LIN Base Address Table
      2. 40.7.2 LIN_REGS Registers
  43. 41Serial Peripheral Interface (SPI)
    1. 41.1 Introduction
      1. 41.1.1 Features
      2. 41.1.2 Block Diagram
    2. 41.2 System-Level Integration
      1. 41.2.1 SPI Module Signals
      2. 41.2.2 Configuring Device Pins
        1. 41.2.2.1 GPIOs Required for High-Speed Mode
      3. 41.2.3 SPI Interrupts
      4. 41.2.4 RTDMA Support
    3. 41.3 SPI Operation
      1. 41.3.1  Introduction to Operation
      2. 41.3.2  Controller Mode
      3. 41.3.3  Peripheral Mode
      4. 41.3.4  Data Format
        1. 41.3.4.1 Transmission of Bit from SPIRXBUF
      5. 41.3.5  Baud Rate Selection
        1. 41.3.5.1 Baud Rate Determination
        2. 41.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
        3. 41.3.5.3 Baud Rate Calculation
      6. 41.3.6  SPI Clocking Schemes
      7. 41.3.7  SPI FIFO Description
      8. 41.3.8  SPI RTDMA Transfers
        1. 41.3.8.1 Transmitting Data Using SPI with RTDMA
        2. 41.3.8.2 Receiving Data Using SPI with RTDMA
      9. 41.3.9  SPI High-Speed Mode
      10. 41.3.10 SPI 3-Wire Mode Description
    4. 41.4 Programming Procedure
      1. 41.4.1 Initialization Upon Reset
      2. 41.4.2 Configuring the SPI
      3. 41.4.3 Configuring the SPI for High-Speed Mode
      4. 41.4.4 Data Transfer Example
      5. 41.4.5 SPI 3-Wire Mode Code Examples
        1. 41.4.5.1 3-Wire Controller Mode Transmit
        2.       1703
          1. 41.4.5.2.1 3-Wire Controller Mode Receive
        3.       1705
          1. 41.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1707
          1. 41.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 41.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 41.5 Software
      1. 41.5.1 SPI Registers to Driverlib Functions
      2. 41.5.2 SPI Examples
        1. 41.5.2.1 SPI Digital Loopback - SINGLE_CORE
        2. 41.5.2.2 SPI Digital Loopback with FIFO Interrupts - SINGLE_CORE
        3. 41.5.2.3 SPI Digital External Loopback without FIFO Interrupts - SINGLE_CORE
        4. 41.5.2.4 SPI Digital External Loopback with FIFO Interrupts - SINGLE_CORE
        5. 41.5.2.5 SPI Digital Loopback with DMA - SINGLE_CORE
    6. 41.6 SPI Registers
      1. 41.6.1 SPI Base Address Table
      2. 41.6.2 SPI_REGS Registers
  44. 42Single Edge Nibble Transmission (SENT)
    1. 42.1 Introduction
      1. 42.1.1 Features
      2. 42.1.2 SENT Related Collateral
    2. 42.2 Advanced Topologies: MTPG
      1. 42.2.1 MTPG Features
      2. 42.2.2 MTPG Description
      3. 42.2.3 Channel Triggers
      4. 42.2.4 Timeout
    3. 42.3 Protocol Description
      1. 42.3.1 Nibble Frame Format
      2. 42.3.2 CRC
      3. 42.3.3 Short Serial Message Format
      4. 42.3.4 Enhanced Serial Message Format
      5. 42.3.5 Enhanced Serial Message Format CRC
      6. 42.3.6 Receive Modes
    4. 42.4 RTDMA Trigger
    5. 42.5 Interrupts Configuration
    6. 42.6 Glitch Filter
    7. 42.7 Software
      1. 42.7.1 SENT Registers to Driverlib Functions
      2. 42.7.2 SENT Examples
        1. 42.7.2.1 SENT Single Sensor - SINGLE_CORE
    8. 42.8 SENT Registers
      1. 42.8.1 SENT Base Address Table
      2. 42.8.2 SENT_CFG Registers
      3. 42.8.3 SENT_MEM Registers
      4. 42.8.4 SENT_MTPG Registers
  45. 43â–º SECURITY PERIPHERALS
    1.     Technical Reference Manual Overview
  46. 44Security Modules
    1. 44.1 Hardware Security Module (HSM)
      1. 44.1.1 HSM Related Collateral
    2. 44.2 Cryptographic Accelerators
  47. 45Revision History

3.13.2 DEV_CFG_REGS Registers

Table 3-20 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses not listed in Table 3-20 should be considered as reserved locations and the register contents should not be modified.

Table 3-20 DEV_CFG_REGS Registers
OffsetAcronymRegister NameProtection
0hDEVCFGLOCK1Lock bit for PERxSYSCONFIG0-31 registersPARITY
4hDEVCFGLOCK2Lock bit for DEVCFG registersPARITY
8hDEVCFGLOCK3Lock bit for PERxSYSCONFIG32-63 registersPARITY
ChDEVCFGLOCK4Lock bit for PERxSYSCONFIG64-95 registersPARITY
10hDEVCFGLOCK5Lock bit for PERxSYSCONFIG96-127 registersPARITY
14hDEVCFGLOCK6Lock bit for PERxSYSCONFIG128-159 registersPARITY
20hPARTIDLLower 32-bit of Device PART Identification NumberPARITY
24hPARTIDHUpper 32-bit of Device PART Identification NumberPARITY
28hREVIDDevice Revision NumberPARITY
1C0hMCUCNF1MCUCNF Capability: EMIF CustomizationPARITY
1C4hMCUCNF2MCUCNF Capability: EPWMPARITY
1CChMCUCNF4MCUCNF Capability: EQEPPARITY
1D8hMCUCNF7MCUCNF Capability: UARTPARITY
1E4hMCUCNF10MCUCNF Capability: CAN, MCANPARITY
1F0hMCUCNF13MCUCNF Capability: AMCUCNFPARITY
1F4hMCUCNF14MCUCNF Capability: CMPSSPARITY
1FChMCUCNF16MCUCNF Capability: DACPARITY
200hMCUCNF17MCUCNF Capability: CLBPARITY
204hMCUCNF18MCUCNF Capability: FSIPARITY
208hMCUCNF19MCUCNF Capability: LINPARITY
218hMCUCNF23MCUCNF Capability: EtherCATPARITY
224hMCUCNF26Device Capability: HSM-Crypto Engines AES, SHA, PKA, TRNGPARITY
238hMCUCNF31Device Capability: HSM-Crypto Engines SM2, SM3, SM4PARITY
2BChMCUCNF64MCUCNF Capability: MCUCNF level, Processing Block, RTDMA CustomizationPARITY
2C0hMCUCNF65MCUCNF Capability: On-chip SRAM CustomizationPARITY
2E4hMCUCNF74MCUCNF Capability: FLC1.B0/B1PARITY
2EChMCUCNF76MCUCNF Capability: FLC1.B2/B3PARITY
2F4hMCUCNF78MCUCNF Capability: FLC1.B4 256KB Data FlashPARITY
2F8hMCUCNF79MCUCNF Capability: FLC2.B0/B1PARITY
300hMCUCNF81MCUCNF Capability: FLC2.B2/B3PARITY
33ChMCUCNFLOCK1Lock bit for MCUCNFx registersPARITY
340hMCUCNFLOCK2Lock bit for MCUCNFx registersPARITY
344hMCUCNFLOCK3Lock bit for MCUCNFx registersPARITY
348hLSENLockstep enable configurationPARITY
37ChEPWMXLINKCFGConfigure which EPWM module instaces are linked in the XLINK schemePARITY
384hSICCONFIGSafety Interconnect(SIC) Configuration - Enable and READY TIMEOUT value
3B0hRSTSTATReset Status register for secondary CPUsPARITY
3B4hLPMSTATLPM Status Register for secondary CPUsPARITY
3CChTAP_STATUSStatus of JTAG State machine & Debugger ConnectPARITY
3D0hTAP_CONTROLDisable TAP controlPARITY
3D4hDEVLIFECYCLEReflect the state of the Device Life Cycle signals reported from the HSMPARITY
47ChSDFMTYPEConfigures SDFM Type for the devicePARITY
4AChSYNCSELECTSync Input and Output Select RegisterPARITY
4B0hADCSOCOUTSELECTExternal ADCSOC Select Register (PWM1-16)PARITY
4B4hADCSOCOUTSELECT1External ADCSOC Select Register (PWM17-32)PARITY
4B8hSYNCSOCLOCKSYNCSEL and ADCSOC Select Lock registerPARITY
4DChHSMTOCPU_STS1HSM to C29x Signal Status1PARITY
4E0hHSMTOCPU_STS2HSM to C29x Signal Status2PARITY
4E4hHSM_SECURE_BOOT_INFO_REG0Status information of the secure boot process HSM to CPU1PARITY
4E8hHSM_SECURE_BOOT_INFO_REG1Status information of the secure boot process HSM to CPU1PARITY
4EChHSM_SECURE_BOOT_INFO_REG2Status information of the secure boot process HSM to CPU1PARITY
4F0hHSM_SECURE_BOOT_INFO_REG3Status information of the secure boot process HSM to CPU1PARITY
4F4hHSM_SECURE_BOOT_INFO_REG4Status information of the secure boot process HSM to CPU1PARITY
4F8hHSM_SECURE_BOOT_INFO_REG5Status information of the secure boot process HSM to CPU1PARITY
4FChHSM_SECURE_BOOT_INFO_REG6Status information of the secure boot process HSM to CPU1PARITY
500hHSM_SECURE_BOOT_INFO_REG7Status information of the secure boot process HSM to CPU1PARITY
504hSOC_SECURE_BOOT_INFO_REG0Status information of the secure boot process CPU1 to HSMPARITY
508hSOC_SECURE_BOOT_INFO_REG1Status information of the secure boot process CPU1 to HSMPARITY
50ChSOC_SECURE_BOOT_INFO_REG2Status information of the secure boot process CPU1 to HSMPARITY
510hSOC_SECURE_BOOT_INFO_REG3Status information of the secure boot process CPU1 to HSMPARITY
514hSOC_SECURE_BOOT_INFO_REG4Status information of the secure boot process CPU1 to HSMPARITY
518hSOC_SECURE_BOOT_INFO_REG5Status information of the secure boot process CPU1 to HSMPARITY
51ChSOC_SECURE_BOOT_INFO_REG6Status information of the secure boot process CPU1 to HSMPARITY
520hSOC_SECURE_BOOT_INFO_REG7Status information of the secure boot process CPU1 to HSMPARITY
524hCLKCFGLOCK1Lock bit for CLKCFG registersPARITY
530hCLKSRCCTL1Clock Source Control register-1PARITY
534hCLKSRCCTL2Clock Source Control register-2PARITY
538hCLKSRCCTL3Clock Source Control register-3PARITY
53ChSYSPLLCTL1SYSPLL Control register-1PARITY
548hSYSPLLMULTSYSPLL Multiplier registerPARITY
54ChSYSPLLSTSSYSPLL Status registerPARITY
564hSYSCLKDIVSELSystem Clock Divider Select registerPARITY
56ChPERCLKDIVSELPeripheral Clock Divider Select registerPARITY
570hXCLKOUTDIVSELXCLKOUT Divider Select registerPARITY
574hHSMCLKDIVSELHSM SYSCLK Divider Select registerPARITY
578hMCANCLKDIVSELMCAN Bit Clock Divider Select registerPARITY
57ChCLBCLKCTLCLB Clocking Control RegisterPARITY
584hMCDCRMissing Clock Detect Control RegisterPARITY
588hX1CNT10-bit Counter on X1 Clock
58ChXTALCRXTAL Control RegisterPARITY
59ChXTALCR2XTAL Control Register for pad initPARITY
5A8hETHERCATCLKCTLEtherCAT Clock ControlPARITY
5AChETHERCATCTLETHERCAT control register.PARITY
5B0hSYNCBUSYPulse Transfer Sync Busy Status registerPARITY
5C0hESMXRSNCTLEnable ESM reset outputs for XRSnPARITY
5C8hEPWM1PER2SYSCONFIG - Peripheral System Configuration for EPWM1PARITY
5CChEPWM2PER3SYSCONFIG - Peripheral System Configuration for EPWM2PARITY
5D0hEPWM3PER4SYSCONFIG - Peripheral System Configuration for EPWM3PARITY
5D4hEPWM4PER5SYSCONFIG - Peripheral System Configuration for EPWM4PARITY
5D8hEPWM5PER6SYSCONFIG - Peripheral System Configuration for EPWM5PARITY
5DChEPWM6PER7SYSCONFIG - Peripheral System Configuration for EPWM6PARITY
5E0hEPWM7PER8SYSCONFIG - Peripheral System Configuration for EPWM7PARITY
5E4hEPWM8PER9SYSCONFIG - Peripheral System Configuration for EPWM8PARITY
5E8hEPWM9PER10SYSCONFIG - Peripheral System Configuration for EPWM9PARITY
5EChEPWM10PER11SYSCONFIG - Peripheral System Configuration for EPWM10PARITY
5F0hEPWM11PER12SYSCONFIG - Peripheral System Configuration for EPWM11PARITY
5F4hEPWM12PER13SYSCONFIG - Peripheral System Configuration for EPWM12PARITY
5F8hEPWM13PER14SYSCONFIG - Peripheral System Configuration for EPWM13PARITY
5FChEPWM14PER15SYSCONFIG - Peripheral System Configuration for EPWM14PARITY
600hEPWM15PER16SYSCONFIG - Peripheral System Configuration for EPWM15PARITY
604hEPWM16PER17SYSCONFIG - Peripheral System Configuration for EPWM16PARITY
608hEPWM17PER18SYSCONFIG - Peripheral System Configuration for EPWM17PARITY
60ChEPWM18PER19SYSCONFIG - Peripheral System Configuration for EPWM18PARITY
614hHRCAL0PER21SYSCONFIG - Peripheral System Configuration for HRCAL0PARITY
618hHRCAL1PER22SYSCONFIG - Peripheral System Configuration for HRCAL1PARITY
61ChHRCAL2PER23SYSCONFIG - Peripheral System Configuration for HRCAL2PARITY
620hECAP1PER24SYSCONFIG - Peripheral System Configuration for ECAP1PARITY
624hECAP2PER25SYSCONFIG - Peripheral System Configuration for ECAP2PARITY
628hECAP3PER26SYSCONFIG - Peripheral System Configuration for ECAP3PARITY
62ChECAP4PER27SYSCONFIG - Peripheral System Configuration for ECAP4PARITY
630hECAP5PER28SYSCONFIG - Peripheral System Configuration for ECAP5PARITY
634hECAP6PER29SYSCONFIG - Peripheral System Configuration for ECAP6PARITY
638hEQEP1PER30SYSCONFIG - Peripheral System Configuration for EQEP1PARITY
63ChEQEP2PER31SYSCONFIG - Peripheral System Configuration for EQEP2PARITY
640hEQEP3PER32SYSCONFIG - Peripheral System Configuration for EQEP3PARITY
644hEQEP4PER33SYSCONFIG - Peripheral System Configuration for EQEP4PARITY
648hEQEP5PER34SYSCONFIG - Peripheral System Configuration for EQEP5PARITY
64ChEQEP6PER35SYSCONFIG - Peripheral System Configuration for EQEP6PARITY
650hSDFM1PER36SYSCONFIG - Peripheral System Configuration for SDFM1PARITY
654hSDFM2PER37SYSCONFIG - Peripheral System Configuration for SDFM2PARITY
658hSDFM3PER38SYSCONFIG - Peripheral System Configuration for SDFM3PARITY
65ChSDFM4PER39SYSCONFIG - Peripheral System Configuration for SDFM4PARITY
660hUARTAPER40SYSCONFIG - Peripheral System Configuration for UARTAPARITY
664hUARTBPER41SYSCONFIG - Peripheral System Configuration for UARTBPARITY
668hUARTCPER42SYSCONFIG - Peripheral System Configuration for UARTCPARITY
66ChUARTDPER43SYSCONFIG - Peripheral System Configuration for UARTDPARITY
670hUARTEPER44SYSCONFIG - Peripheral System Configuration for UARTEPARITY
674hUARTFPER45SYSCONFIG - Peripheral System Configuration for UARTFPARITY
678hSPIAPER46SYSCONFIG - Peripheral System Configuration for SPIAPARITY
67ChSPIBPER47SYSCONFIG - Peripheral System Configuration for SPIBPARITY
680hSPICPER48SYSCONFIG - Peripheral System Configuration for SPICPARITY
684hSPIDPER49SYSCONFIG - Peripheral System Configuration for SPIDPARITY
688hSPIEPER50SYSCONFIG - Peripheral System Configuration for SPIEPARITY
68ChI2CAPER51SYSCONFIG - Peripheral System Configuration for I2CAPARITY
690hI2CBPER52SYSCONFIG - Peripheral System Configuration for I2CBPARITY
694hPMBUSAPER53SYSCONFIG - Peripheral System Configuration for PMBUSAPARITY
698hLINAPER54SYSCONFIG - Peripheral System Configuration for LINAPARITY
69ChLINBPER55SYSCONFIG - Peripheral System Configuration for LINBPARITY
6A0hMCANAPER56SYSCONFIG - Peripheral System Configuration for MCANAPARITY
6A4hMCANBPER57SYSCONFIG - Peripheral System Configuration for MCANBPARITY
6A8hMCANCPER58SYSCONFIG - Peripheral System Configuration for MCANCPARITY
6AChMCANDPER59SYSCONFIG - Peripheral System Configuration for MCANDPARITY
6B0hMCANEPER60SYSCONFIG - Peripheral System Configuration for MCANEPARITY
6B4hMCANFPER61SYSCONFIG - Peripheral System Configuration for MCANFPARITY
6B8hADCAPER62SYSCONFIG - Peripheral System Configuration for ADCAPARITY
6BChADCBPER63SYSCONFIG - Peripheral System Configuration for ADCBPARITY
6C0hADCCPER64SYSCONFIG - Peripheral System Configuration for ADCCPARITY
6C4hADCDPER65SYSCONFIG - Peripheral System Configuration for ADCDPARITY
6C8hADCEPER66SYSCONFIG - Peripheral System Configuration for ADCEPARITY
6CChCMPSS1PER67SYSCONFIG - Peripheral System Configuration for CMPSS1PARITY
6D0hCMPSS2PER68SYSCONFIG - Peripheral System Configuration for CMPSS2PARITY
6D4hCMPSS3PER69SYSCONFIG - Peripheral System Configuration for CMPSS3PARITY
6D8hCMPSS4PER70SYSCONFIG - Peripheral System Configuration for CMPSS4PARITY
6DChCMPSS5PER71SYSCONFIG - Peripheral System Configuration for CMPSS5PARITY
6E0hCMPSS6PER72SYSCONFIG - Peripheral System Configuration for CMPSS6PARITY
6E4hCMPSS7PER73SYSCONFIG - Peripheral System Configuration for CMPSS7PARITY
6E8hCMPSS8PER74SYSCONFIG - Peripheral System Configuration for CMPSS8PARITY
6EChCMPSS9PER75SYSCONFIG - Peripheral System Configuration for CMPSS9PARITY
6F0hCMPSS10PER76SYSCONFIG - Peripheral System Configuration for CMPSS10PARITY
6F4hCMPSS11PER77SYSCONFIG - Peripheral System Configuration for CMPSS11PARITY
6F8hCMPSS12PER78SYSCONFIG - Peripheral System Configuration for CMPSS12PARITY
6FChDACAPER79SYSCONFIG - Peripheral System Configuration for DACAPARITY
700hDACBPER80SYSCONFIG - Peripheral System Configuration for DACBPARITY
704hCLB1PER81SYSCONFIG - Peripheral System Configuration for CLB1PARITY
708hCLB2PER82SYSCONFIG - Peripheral System Configuration for CLB2PARITY
70ChCLB3PER83SYSCONFIG - Peripheral System Configuration for CLB3PARITY
710hCLB4PER84SYSCONFIG - Peripheral System Configuration for CLB4PARITY
714hCLB5PER85SYSCONFIG - Peripheral System Configuration for CLB5PARITY
718hCLB6PER86SYSCONFIG - Peripheral System Configuration for CLB6PARITY
71ChFSITXAPER87SYSCONFIG - Peripheral System Configuration for FSITXAPARITY
720hFSITXBPER88SYSCONFIG - Peripheral System Configuration for FSITXBPARITY
724hFSITXCPER89SYSCONFIG - Peripheral System Configuration for FSITXCPARITY
728hFSITXDPER90SYSCONFIG - Peripheral System Configuration for FSITXDPARITY
72ChFSIRXAPER91SYSCONFIG - Peripheral System Configuration for FSIRXAPARITY
730hFSIRXBPER92SYSCONFIG - Peripheral System Configuration for FSIRXBPARITY
734hFSIRXCPER93SYSCONFIG - Peripheral System Configuration for FSIRXCPARITY
738hFSIRXDPER94SYSCONFIG - Peripheral System Configuration for FSIRXDPARITY
73ChDCC1PER95SYSCONFIG - Peripheral System Configuration for DCC1PARITY
740hDCC2PER96SYSCONFIG - Peripheral System Configuration for DCC2PARITY
744hDCC3PER97SYSCONFIG - Peripheral System Configuration for DCC3PARITY
748hETHERCATAPER98SYSCONFIG - Peripheral System Configuration for ETHERCATAPARITY
74ChEPG1PER99SYSCONFIG - Peripheral System Configuration for EPG1PARITY
750hSENT1PER100SYSCONFIG - Peripheral System Configuration for SENT1PARITY
754hSENT2PER101SYSCONFIG - Peripheral System Configuration for SENT2PARITY
758hSENT3PER102SYSCONFIG - Peripheral System Configuration for SENT3PARITY
75ChSENT4PER103SYSCONFIG - Peripheral System Configuration for SENT4PARITY
760hSENT5PER104SYSCONFIG - Peripheral System Configuration for SENT5PARITY
764hSENT6PER105SYSCONFIG - Peripheral System Configuration for SENT6PARITY
768hADCCHECKER1PER106SYSCONFIG - Peripheral System Configuration for ADCCHECKER1PARITY
76ChADCCHECKER2PER107SYSCONFIG - Peripheral System Configuration for ADCCHECKER2PARITY
770hADCCHECKER3PER108SYSCONFIG - Peripheral System Configuration for ADCCHECKER3PARITY
774hADCCHECKER4PER109SYSCONFIG - Peripheral System Configuration for ADCCHECKER4PARITY
778hADCCHECKER5PER110SYSCONFIG - Peripheral System Configuration for ADCCHECKER5PARITY
77ChADCCHECKER6PER111SYSCONFIG - Peripheral System Configuration for ADCCHECKER6PARITY
780hADCCHECKER7PER112SYSCONFIG - Peripheral System Configuration for ADCCHECKER7PARITY
784hADCCHECKER8PER113SYSCONFIG - Peripheral System Configuration for ADCCHECKER8PARITY
788hADCCHECKER9PER114SYSCONFIG - Peripheral System Configuration for ADCCHECKER9PARITY
78ChADCCHECKER10PER115SYSCONFIG - Peripheral System Configuration for ADCCHECKER10PARITY
790hADCSEAGGRCPU1PER116SYSCONFIG - Peripheral System Configuration for ADCSEAGGRCPU1PARITY
794hADCSEAGGRCPU2PER117SYSCONFIG - Peripheral System Configuration for ADCSEAGGRCPU2PARITY
798hADCSEAGGRCPU3PER118SYSCONFIG - Peripheral System Configuration for ADCSEAGGRCPU3PARITY
7A8hRTDMA1CHPER122SYSCONFIG - Peripheral System Configuration for RTDMA1CHPARITY
7AChRTDMA2CHPER123SYSCONFIG - Peripheral System Configuration for RTDMA2CHPARITY
7B0hWADI1PER124SYSCONFIG - Peripheral System Configuration for WADI1PARITY
7B4hWADI2PER125SYSCONFIG - Peripheral System Configuration for WADI2PARITY
7B8hINPUTXBARFlagsPER126SYSCONFIG - Peripheral System Configuration for INPUTXBARFlagsPARITY
7BChOUTPUTXBARFlagsPER127SYSCONFIG - Peripheral System Configuration for OUTPUTXBARFlagsPARITY
7C0hDLTFIFORegsPER128SYSCONFIG - Peripheral System Configuration for DLTFIFORegsPARITY
7C4hADC_GLOBAL_REGSPER129SYSCONFIG - Peripheral System Configuration for ADC_GLOBAL_REGSPARITY
7C8hError_AggregatorPER130SYSCONFIG - Peripheral System Configuration for Error_AggregatorPARITY
7CChESMPER131SYSCONFIG - Peripheral System Configuration for ESM ESMCPU1/2/3 and ESMSYSPARITY
7E4hPARITY_TESTEnables parity test

Complex bit access types are encoded to fit into small table cells. Table 3-21 shows the codes that are used for access types in this section.

Table 3-21 DEV_CFG_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
WOnceW
Once		Write
Write once
WSonceW
Sonce		Write
Set once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

3.13.2.1 DEVCFGLOCK1 Register (Offset = 0h) [Reset = 00000000h]

DEVCFGLOCK1 is shown in Figure 3-28 and described in Table 3-22.

Return to the Summary Table.

Lock bit for CPUSELx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-28 DEVCFGLOCK1 Register
3130292827262524
PER31SYSCONFIGPER30SYSCONFIGPER29SYSCONFIGPER28SYSCONFIGPER27SYSCONFIGPER26SYSCONFIGPER25SYSCONFIGPER24SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
PER23SYSCONFIGPER22SYSCONFIGPER21SYSCONFIGPER20SYSCONFIGPER19SYSCONFIGPER18SYSCONFIGPER17SYSCONFIGPER16SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
PER15SYSCONFIGPER14SYSCONFIGPER13SYSCONFIGPER12SYSCONFIGPER11SYSCONFIGPER10SYSCONFIGPER9SYSCONFIGPER8SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
PER7SYSCONFIGPER6SYSCONFIGPER5SYSCONFIGPER4SYSCONFIGPER3SYSCONFIGPER2SYSCONFIGPER1SYSCONFIGPER0SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-22 DEVCFGLOCK1 Register Field Descriptions
BitFieldTypeResetDescription
31PER31SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

30PER30SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

29PER29SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

28PER28SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

27PER27SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

26PER26SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

25PER25SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

24PER24SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

23PER23SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

22PER22SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

21PER21SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

20PER20SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

19PER19SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

18PER18SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

17PER17SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

16PER16SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

15PER15SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

14PER14SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

13PER13SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

12PER12SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

11PER11SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

10PER10SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

9PER9SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

8PER8SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

7PER7SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

6PER6SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

5PER5SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

4PER4SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3PER3SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

2PER2SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

1PER1SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

0PER0SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3.13.2.2 DEVCFGLOCK2 Register (Offset = 4h) [Reset = 00000000h]

DEVCFGLOCK2 is shown in Figure 3-29 and described in Table 3-23.

Return to the Summary Table.

Lock bit for DEVCFG registers
Note:
[1] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
[2] Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-29 DEVCFGLOCK2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
PCLKCR22ETHERCATCTLRESERVEDLSENSICCONFIGRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-23 DEVCFGLOCK2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7PCLKCR22R/WSonce0h0 Allows write to PCLKCR22 register
1 Blocks write to PCLKCR22 register

Reset type: CPU1.SYSRSn

6ETHERCATCTLR/WSonce0h0 Allows write to ETHERCATCTL register
1 Blocks write to ETHERCATCTL register

Reset type: CPU1.SYSRSn

5RESERVEDR/WSonce0hReserved
4LSENR/WSonce0h0 Allows write to LSEN register
1 Blocks write to LSEN register

Reset type: CPU1.SYSRSn

3SICCONFIGR/WSonce0h0 Allows write to SICCONFIG register
1 Blocks write to SICCONFIG register

Reset type: CPU1.SYSRSn

2RESERVEDR/WSonce0hReserved
1RESERVEDR/WSonce0hReserved
0RESERVEDR/WSonce0hReserved

3.13.2.3 DEVCFGLOCK3 Register (Offset = 8h) [Reset = 00000000h]

DEVCFGLOCK3 is shown in Figure 3-30 and described in Table 3-24.

Return to the Summary Table.

Lock bit for DEVCFG registers
Note:
[1] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
[2] Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-30 DEVCFGLOCK3 Register
3130292827262524
PER63SYSCONFIGPER62SYSCONFIGPER61SYSCONFIGPER60SYSCONFIGPER59SYSCONFIGPER58SYSCONFIGPER57SYSCONFIGPER56SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
PER55SYSCONFIGPER54SYSCONFIGPER53SYSCONFIGPER52SYSCONFIGPER51SYSCONFIGPER50SYSCONFIGPER49SYSCONFIGPER48SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
PER47SYSCONFIGPER46SYSCONFIGPER45SYSCONFIGPER44SYSCONFIGPER43SYSCONFIGPER42SYSCONFIGPER41SYSCONFIGPER40SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
PER39SYSCONFIGPER38SYSCONFIGPER37SYSCONFIGPER36SYSCONFIGPER35SYSCONFIGPER34SYSCONFIGPER33SYSCONFIGPER32SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-24 DEVCFGLOCK3 Register Field Descriptions
BitFieldTypeResetDescription
31PER63SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

30PER62SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

29PER61SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

28PER60SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

27PER59SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

26PER58SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

25PER57SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

24PER56SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

23PER55SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

22PER54SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

21PER53SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

20PER52SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

19PER51SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

18PER50SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

17PER49SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

16PER48SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

15PER47SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

14PER46SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

13PER45SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

12PER44SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

11PER43SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

10PER42SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

9PER41SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

8PER40SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

7PER39SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

6PER38SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

5PER37SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

4PER36SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3PER35SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

2PER34SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

1PER33SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

0PER32SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3.13.2.4 DEVCFGLOCK4 Register (Offset = Ch) [Reset = 00000000h]

DEVCFGLOCK4 is shown in Figure 3-31 and described in Table 3-25.

Return to the Summary Table.

Lock bit for DEVCFG registers
Note:
[1] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
[2] Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-31 DEVCFGLOCK4 Register
3130292827262524
PER95SYSCONFIGPER94SYSCONFIGPER93SYSCONFIGPER92SYSCONFIGPER91SYSCONFIGPER90SYSCONFIGPER89SYSCONFIGPER88SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
PER87SYSCONFIGPER86SYSCONFIGPER85SYSCONFIGPER84SYSCONFIGPER83SYSCONFIGPER82SYSCONFIGPER81SYSCONFIGPER80SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
PER79SYSCONFIGPER78SYSCONFIGPER77SYSCONFIGPER76SYSCONFIGPER75SYSCONFIGPER74SYSCONFIGPER73SYSCONFIGPER72SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
PER71SYSCONFIGPER70SYSCONFIGPER69SYSCONFIGPER68SYSCONFIGPER67SYSCONFIGPER66SYSCONFIGPER65SYSCONFIGPER64SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-25 DEVCFGLOCK4 Register Field Descriptions
BitFieldTypeResetDescription
31PER95SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

30PER94SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

29PER93SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

28PER92SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

27PER91SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

26PER90SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

25PER89SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

24PER88SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

23PER87SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

22PER86SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

21PER85SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

20PER84SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

19PER83SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

18PER82SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

17PER81SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

16PER80SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

15PER79SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

14PER78SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

13PER77SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

12PER76SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

11PER75SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

10PER74SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

9PER73SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

8PER72SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

7PER71SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

6PER70SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

5PER69SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

4PER68SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3PER67SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

2PER66SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

1PER65SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

0PER64SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3.13.2.5 DEVCFGLOCK5 Register (Offset = 10h) [Reset = 00000000h]

DEVCFGLOCK5 is shown in Figure 3-32 and described in Table 3-26.

Return to the Summary Table.

Lock bit for DEVCFG registers
Note:
[1] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
[2] Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-32 DEVCFGLOCK5 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDPER120SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
2322212019181716
PER119SYSCONFIGPER118SYSCONFIGPER117SYSCONFIGPER116SYSCONFIGPER115SYSCONFIGPER114SYSCONFIGPER113SYSCONFIGPER112SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
PER111SYSCONFIGPER110SYSCONFIGPER109SYSCONFIGPER108SYSCONFIGPER107SYSCONFIGPER106SYSCONFIGPER105SYSCONFIGPER104SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
PER103SYSCONFIGPER102SYSCONFIGPER101SYSCONFIGPER100SYSCONFIGPER99SYSCONFIGPER98SYSCONFIGPER97SYSCONFIGPER96SYSCONFIG
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-26 DEVCFGLOCK5 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WSonce0hReserved
30RESERVEDR/WSonce0hReserved
29RESERVEDR/WSonce0hReserved
28RESERVEDR/WSonce0hReserved
27RESERVEDR/WSonce0hReserved
26RESERVEDR/WSonce0hReserved
25RESERVEDR/WSonce0hReserved
24PER120SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

23PER119SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

22PER118SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

21PER117SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

20PER116SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

19PER115SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

18PER114SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

17PER113SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

16PER112SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

15PER111SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

14PER110SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

13PER109SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

12PER108SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

11PER107SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

10PER106SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

9PER105SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

8PER104SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

7PER103SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

6PER102SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

5PER101SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

4PER100SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3PER99SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

2PER98SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

1PER97SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

0PER96SYSCONFIGR/WSonce0h0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3.13.2.6 DEVCFGLOCK6 Register (Offset = 14h) [Reset = 00000000h]

DEVCFGLOCK6 is shown in Figure 3-33 and described in Table 3-27.

Return to the Summary Table.

Lock bit for DEVCFG registers
Note:
[1] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
[2] Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-33 DEVCFGLOCK6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-27 DEVCFGLOCK6 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR-00hReserved
6RESERVEDR/WSonce0hReserved
5RESERVEDR/WSonce0hReserved
4RESERVEDR/WSonce0hReserved
3RESERVEDR/WSonce0hReserved
2RESERVEDR/WSonce0hReserved
1RESERVEDR/WSonce0hReserved
0RESERVEDR/WSonce0hReserved

3.13.2.7 PARTIDL Register (Offset = 20h) [Reset = 00XXXXX0h]

PARTIDL is shown in Figure 3-34 and described in Table 3-28.

Return to the Summary Table.

Lower 32-bit of Device PART Identification Number

Figure 3-34 PARTIDL Register
3130292827262524
PARTID_FORMAT_REVRESERVED
R-0hR-0h
2322212019181716
FLASH_SIZE
R-XXh
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDPIN_COUNT
R-0hR-XhR-0hR-XhR-Xh
76543210
QUALRESERVEDRESERVEDRESERVED
R-XhR-0hR-0hR-0h
Table 3-28 PARTIDL Register Field Descriptions
BitFieldTypeResetDescription
31-28PARTID_FORMAT_REVR0h0 = Gen3
1 = F29x Devices

Reset type: PORESETn

27-24RESERVEDR0hReserved
23-16FLASH_SIZERXXhFlash Size

0x3=1MB
0x4=2MB/4 Banks (F29P58x)
0x5=2MB/8 Banks (F29H85x)
0x6=4MB
Others=Reserved

Reset type: PORESETn

15RESERVEDR0hReserved
14-13RESERVEDRXhReserved
12RESERVEDR0hReserved
11RESERVEDRXhReserved
10-8PIN_COUNTRXh0 = Reserved
1 = 100 pin QFP
2 = 144 pin QFP
3 = 176 pin QFP
4 = 256 pin BGA
5,6,7 = Reserved

Reset type: PORESETn

7-6QUALRXh0 = Engineering sample (TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)

Reset type: PORESETn

5RESERVEDR0hReserved
4-3RESERVEDR0hReserved
2-0RESERVEDR0hReserved

3.13.2.8 PARTIDH Register (Offset = 24h) [Reset = 0DXX0500h]

PARTIDH is shown in Figure 3-35 and described in Table 3-29.

Return to the Summary Table.

Upper 32-bit of Device PART Identification Number

Figure 3-35 PARTIDH Register
31302928272625242322212019181716
DEVICE_CLASS_IDPARTNO
R-DhR-XXh
1514131211109876543210
FAMILYRESERVEDRESERVED
R-5hR-0hR-0h
Table 3-29 PARTIDH Register Field Descriptions
BitFieldTypeResetDescription
31-24DEVICE_CLASS_IDRDhDevice class ID
Refer to the device specific datasheet for more information

Reset type: PORESETn

23-16PARTNORXXhPart Number Designator
Refer to the device specific datasheet for more information

Reset type: PORESETn

15-8FAMILYR5hDevice Family
This field categorizes the device to one of the C2000 device families.

Reset type: PORESETn

7-4RESERVEDR0hReserved
3-0RESERVEDR0hReserved

3.13.2.9 REVID Register (Offset = 28h) [Reset = 00000000h]

REVID is shown in Figure 3-36 and described in Table 3-30.

Return to the Summary Table.

Device Revision Number

Figure 3-36 REVID Register
313029282726252423222120191817161514131211109876543210
RESERVEDREVID
R-0-0hR/WOnce-0h
Table 3-30 REVID Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0REVIDR/WOnce0hDevice Revision ID. Loaded from flash trim sector by boot rom. Reset value is die-specific.

Reset type: XRSn

3.13.2.10 MCUCNF1 Register (Offset = 1C0h) [Reset = 0000000Xh]

MCUCNF1 is shown in Figure 3-37 and described in Table 3-31.

Return to the Summary Table.

MCUCNF Capability: EMIF Customization

Figure 3-37 MCUCNF1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDEMIF1
R-0-0hR-XhR-Xh
Table 3-31 MCUCNF1 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1RESERVEDRXhReserved
0EMIF1RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.11 MCUCNF2 Register (Offset = 1C4h) [Reset = 000XXXXXh]

MCUCNF2 is shown in Figure 3-38 and described in Table 3-32.

Return to the Summary Table.

MCUCNF Capability: EPWM

Figure 3-38 MCUCNF2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDEPWM18EPWM17
R-0-0hR-XhR-Xh
15141312111098
EPWM16EPWM15EPWM14EPWM13EPWM12EPWM11EPWM10EPWM9
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
76543210
EPWM8EPWM7EPWM6EPWM5EPWM4EPWM3EPWM2EPWM1
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
Table 3-32 MCUCNF2 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17EPWM18RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

16EPWM17RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

15EPWM16RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

14EPWM15RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

13EPWM14RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

12EPWM13RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

11EPWM12RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

10EPWM11RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

9EPWM10RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

8EPWM9RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

7EPWM8RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

6EPWM7RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

5EPWM6RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4EPWM5RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3EPWM4RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2EPWM3RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1EPWM2RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0EPWM1RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.12 MCUCNF4 Register (Offset = 1CCh) [Reset = 000000XXh]

MCUCNF4 is shown in Figure 3-39 and described in Table 3-33.

Return to the Summary Table.

MCUCNF Capability: EQEP

Figure 3-39 MCUCNF4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDEQEP6EQEP5EQEP4EQEP3EQEP2EQEP1
R-0-0hR-XhR-XhR-XhR-XhR-XhR-Xh
Table 3-33 MCUCNF4 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5EQEP6RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4EQEP5RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3EQEP4RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2EQEP3RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1EQEP2RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0EQEP1RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.13 MCUCNF7 Register (Offset = 1D8h) [Reset = 00XX001Xh]

MCUCNF7 is shown in Figure 3-40 and described in Table 3-34.

Return to the Summary Table.

MCUCNF Capability: UART

Figure 3-40 MCUCNF7 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDUART_FUART_EUART_DUART_CUART_BUART_A
R-0-0hR-XhR-XhR-XhR-XhR-XhR-Xh
15141312111098
RESERVED
R-0-1h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-1hR-XhR-XhR-XhR-Xh
Table 3-34 MCUCNF7 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR-00hReserved
21UART_FRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

20UART_ERXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

19UART_DRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

18UART_CRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

17UART_BRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

16UART_ARXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

15-4RESERVEDR-01hReserved
3RESERVEDRXhReserved
2RESERVEDRXhReserved
1RESERVEDRXhReserved
0RESERVEDRXhReserved

3.13.2.14 MCUCNF10 Register (Offset = 1E4h) [Reset = 00000XXXh]

MCUCNF10 is shown in Figure 3-41 and described in Table 3-35.

Return to the Summary Table.

MCUCNF Capability: CAN, MCAN

Figure 3-41 MCUCNF10 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDMCAN_FMCAN_E
R-0-0hR-XhR-Xh
76543210
MCAN_DMCAN_CMCAN_BMCAN_ARESERVEDRESERVEDRESERVEDRESERVED
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
Table 3-35 MCUCNF10 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR-00hReserved
9MCAN_FRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

8MCAN_ERXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

7MCAN_DRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

6MCAN_CRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

5MCAN_BRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4MCAN_ARXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3RESERVEDRXhReserved
2RESERVEDRXhReserved
1RESERVEDRXhReserved
0RESERVEDRXhReserved

3.13.2.15 MCUCNF13 Register (Offset = 1F0h) [Reset = 0000001Fh]

MCUCNF13 is shown in Figure 3-42 and described in Table 3-36.

Return to the Summary Table.

MCUCNF Capability: AMCUCNF

Figure 3-42 MCUCNF13 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDADC_EADC_DADC_CADC_BADC_A
R-0-0hR/W-0hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 3-36 MCUCNF13 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR/W0hReserved
4ADC_ER/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3ADC_DR/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2ADC_CR/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1ADC_BR/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0ADC_AR/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.16 MCUCNF14 Register (Offset = 1F4h) [Reset = 00000FFFh]

MCUCNF14 is shown in Figure 3-43 and described in Table 3-37.

Return to the Summary Table.

MCUCNF Capability: CMPSS

Figure 3-43 MCUCNF14 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDCMPSS12CMPSS11CMPSS10CMPSS9
R-0-0hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
CMPSS8CMPSS7CMPSS6CMPSS5CMPSS4CMPSS3CMPSS2CMPSS1
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
Table 3-37 MCUCNF14 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11CMPSS12R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

10CMPSS11R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

9CMPSS10R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

8CMPSS9R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

7CMPSS8R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

6CMPSS7R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

5CMPSS6R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4CMPSS5R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3CMPSS4R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2CMPSS3R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1CMPSS2R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0CMPSS1R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.17 MCUCNF16 Register (Offset = 1FCh) [Reset = 00030000h]

MCUCNF16 is shown in Figure 3-44 and described in Table 3-38.

Return to the Summary Table.

MCUCNF Capability: DAC

Figure 3-44 MCUCNF16 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVEDDAC_BDAC_A
R-0-0hR/W-0hR/W-0hR/W-1hR/W-1h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-38 MCUCNF16 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17DAC_BR/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

16DAC_AR/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.13.2.18 MCUCNF17 Register (Offset = 200h) [Reset = X0000000h]

MCUCNF17 is shown in Figure 3-45 and described in Table 3-39.

Return to the Summary Table.

MCUCNF Capability: CLB

Figure 3-45 MCUCNF17 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLB6CLB5CLB4CLB3CLB2CLB1
R-0hR-0hR-0hR-XhR-XhR-XhR-Xh
Table 3-39 MCUCNF17 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5CLB6R0h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4CLB5R0h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3CLB4RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2CLB3RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1CLB2RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0CLB1RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.19 MCUCNF18 Register (Offset = 204h) [Reset = 0000000Xh]

MCUCNF18 is shown in Figure 3-46 and described in Table 3-40.

Return to the Summary Table.

MCUCNF Capability: FSI

Figure 3-46 MCUCNF18 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDFSIRX_DFSIRX_CFSIRX_BFSIRX_A
R-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDFSITX_DFSITX_CFSITX_BFSITX_A
R-0-0hR-XhR-XhR-XhR-Xh
Table 3-40 MCUCNF18 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19FSIRX_DR0h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

18FSIRX_CR0h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

17FSIRX_BR0h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

16FSIRX_AR0h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

15-4RESERVEDR-00hReserved
3FSITX_DRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2FSITX_CRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1FSITX_BRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0FSITX_ARXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.20 MCUCNF19 Register (Offset = 208h) [Reset = X0000000h]

MCUCNF19 is shown in Figure 3-47 and described in Table 3-41.

Return to the Summary Table.

MCUCNF Capability: LIN

Figure 3-47 MCUCNF19 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDLIN_BLIN_A
R-0hR-XhR-XhR-XhR-Xh
Table 3-41 MCUCNF19 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3RESERVEDRXhReserved
2RESERVEDRXhReserved
1LIN_BRXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0LIN_ARXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.21 MCUCNF23 Register (Offset = 218h) [Reset = 0000000Xh]

MCUCNF23 is shown in Figure 3-48 and described in Table 3-42.

Return to the Summary Table.

MCUCNF Capability: EtherCAT

Figure 3-48 MCUCNF23 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDETHERCAT
R-0-0hR-Xh
Table 3-42 MCUCNF23 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0ETHERCATRXhETHERCAT :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.22 MCUCNF26 Register (Offset = 224h) [Reset = 00041041h]

MCUCNF26 is shown in Figure 3-49 and described in Table 3-43.

Return to the Summary Table.

Device Capability: HSM-Crypto Engines AES, SHA, PKA, TRNG

Figure 3-49 MCUCNF26 Register
313029282726252423222120191817161514131211109876543210
RESERVEDTRNGPKASHAAES
R-0hR/W-1hR/W-1hR/W-1hR/W-1h
Table 3-43 MCUCNF26 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-18TRNGR/W1h6'b1111111 : Module disabled
'others' : Module enabled

Reset type: PORESETn

17-12PKAR/W1h6'b1111111 : Module disabled
'others' : Module enabled

Reset type: PORESETn

11-6SHAR/W1h6'b1111111 : Module disabled
'others' : Module enabled

Reset type: PORESETn

5-0AESR/W1h6'b1111111 : AES disabled
6'b101010 : AES enabled without counter measures
'others' : AES enabled with counter measures

Reset type: PORESETn

3.13.2.23 MCUCNF31 Register (Offset = 238h) [Reset = 00001041h]

MCUCNF31 is shown in Figure 3-50 and described in Table 3-44.

Return to the Summary Table.

Device Capability: HSM-Crypto Engines SM2, SM3, SM4

Figure 3-50 MCUCNF31 Register
313029282726252423222120191817161514131211109876543210
RESERVEDSM4SM3SM2
R-0hR/W-1hR/W-1hR/W-1h
Table 3-44 MCUCNF31 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-12SM4R/W1h6'b1111111 : Module disabled
'others' : Module enabled

Reset type: PORESETn

11-6SM3R/W1h6'b1111111 : Module disabled
'others' : Module enabled

Reset type: PORESETn

5-0SM2R/W1h6'b1111111 : Module disabled
'others' : Module enabled

Reset type: PORESETn

3.13.2.24 MCUCNF64 Register (Offset = 2BCh) [Reset = 0000001Xh]

MCUCNF64 is shown in Figure 3-51 and described in Table 3-45.

Return to the Summary Table.

MCUCNF Capability: MCUCNF level, Processing Block, RTDMA Customization

Figure 3-51 MCUCNF64 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDCPU3CPU2RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-1hR/W-1hR/W-0hR/W-0hR-Xh
Table 3-45 MCUCNF64 Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR-00hReserved
10RESERVEDR/W0hReserved
9RESERVEDR/W0hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4CPU3R/W1hCPU Present
0: CPU3SS is not present
1: CPU3SS is present

Reset type: PORESETn

3CPU2R/W1hCPU Present
0: CPU2SS is not present
1: CPU2SS is present

Reset type: PORESETn

2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDRXhReserved

3.13.2.25 MCUCNF65 Register (Offset = 2C0h) [Reset = 0FFFFF3Xh]

MCUCNF65 is shown in Figure 3-52 and described in Table 3-46.

Return to the Summary Table.

MCUCNF Capability: On-chip SRAM Customization

Figure 3-52 MCUCNF65 Register
3130292827262524
RESERVEDRESERVEDRESERVEDRESERVEDCDA11CDA10CDA9CDA8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-1hR/W-1hR/W-1h
2322212019181716
CDA7CDA6CDA5CDA4CDA3CDA2CDA1CDA0
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
15141312111098
LDA7LDA6LDA5LDA4LDA3LDA2LDA1LDA0
R/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1hR/W-1h
76543210
RESERVEDRESERVEDLPA1LPA0RESERVEDRESERVEDCPA1CPA0
R-0-0hR-0-0hR/W-1hR/W-1hR-0-0hR-0-0hR/W-1hR-Xh
Table 3-46 MCUCNF65 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/W0hReserved
30RESERVEDR/W0hReserved
29RESERVEDR/W0hReserved
28RESERVEDR/W0hReserved
27CDA11R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

26CDA10R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

25CDA9R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

24CDA8R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

23CDA7R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

22CDA6R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

21CDA5R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

20CDA4R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

19CDA3R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

18CDA2R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

17CDA1R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

16CDA0R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

15LDA7R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

14LDA6R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

13LDA5R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

12LDA4R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

11LDA3R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

10LDA2R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

9LDA1R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

8LDA0R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

7RESERVEDR-00hReserved
6RESERVEDR-00hReserved
5LPA1R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4LPA0R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3RESERVEDR-00hReserved
2RESERVEDR-00hReserved
1CPA1R/W1h 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0CPA0RXh 0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.13.2.26 MCUCNF74 Register (Offset = 2E4h) [Reset = 0000XXXXh]

MCUCNF74 is shown in Figure 3-53 and described in Table 3-47.

Return to the Summary Table.

MCUCNF Capability: FLC1.B0/B1

Figure 3-53 MCUCNF74 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
SECT255_240SECT239_224SECT223_208SECT207_192SECT191_176SECT175_160SECT159_144SECT143_128
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
Table 3-47 MCUCNF74 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15SECT255_240RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

14SECT239_224RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

13SECT223_208RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

12SECT207_192RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

11SECT191_176RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

10SECT175_160RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

9SECT159_144RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

8SECT143_128RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

7SECT127_112RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXhFLC1.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.13.2.27 MCUCNF76 Register (Offset = 2ECh) [Reset = 0000XXXXh]

MCUCNF76 is shown in Figure 3-54 and described in Table 3-48.

Return to the Summary Table.

MCUCNF Capability: FLC1.B2/B3

Figure 3-54 MCUCNF76 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
SECT255_240SECT239_224SECT223_208SECT207_192SECT191_176SECT175_160SECT159_144SECT143_128
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
Table 3-48 MCUCNF76 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15SECT255_240RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

14SECT239_224RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

13SECT223_208RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

12SECT207_192RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

11SECT191_176RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

10SECT175_160RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

9SECT159_144RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

8SECT143_128RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

7SECT127_112RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXhFLC1.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.13.2.28 MCUCNF78 Register (Offset = 2F4h) [Reset = 0000XXXXh]

MCUCNF78 is shown in Figure 3-55 and described in Table 3-49.

Return to the Summary Table.

MCUCNF Capability: FLC1.B4 256KB Data Flash

Figure 3-55 MCUCNF78 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
Table 3-49 MCUCNF78 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDRXhReserved
14RESERVEDRXhReserved
13RESERVEDRXhReserved
12RESERVEDRXhReserved
11RESERVEDRXhReserved
10RESERVEDRXhReserved
9RESERVEDRXhReserved
8RESERVEDRXhReserved
7SECT127_112RXhFLC1.B4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXhFLC1.B4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXhFLC1.B4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXhFLC1.B4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXhFLC1.B4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXhFLC1.B4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXhFLC1.B4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXhFLC1.B4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.13.2.29 MCUCNF79 Register (Offset = 2F8h) [Reset = 0000XXXXh]

MCUCNF79 is shown in Figure 3-56 and described in Table 3-50.

Return to the Summary Table.

MCUCNF Capability: FLC2.B0/B1

Figure 3-56 MCUCNF79 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
SECT255_240SECT239_224SECT223_208SECT207_192SECT191_176SECT175_160SECT159_144SECT143_128
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
Table 3-50 MCUCNF79 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15SECT255_240RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

14SECT239_224RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

13SECT223_208RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

12SECT207_192RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

11SECT191_176RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

10SECT175_160RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

9SECT159_144RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

8SECT143_128RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

7SECT127_112RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXhFLC2.B0/B1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.13.2.30 MCUCNF81 Register (Offset = 300h) [Reset = 0000XXXXh]

MCUCNF81 is shown in Figure 3-57 and described in Table 3-51.

Return to the Summary Table.

MCUCNF Capability: FLC2.B2/B3

Figure 3-57 MCUCNF81 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
SECT255_240SECT239_224SECT223_208SECT207_192SECT191_176SECT175_160SECT159_144SECT143_128
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XhR-XhR-XhR-XhR-XhR-XhR-XhR-Xh
Table 3-51 MCUCNF81 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15SECT255_240RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

14SECT239_224RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

13SECT223_208RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

12SECT207_192RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

11SECT191_176RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

10SECT175_160RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

9SECT159_144RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

8SECT143_128RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

7SECT127_112RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXhFLC2.B2/B3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.13.2.31 MCUCNFLOCK1 Register (Offset = 33Ch) [Reset = 00000000h]

MCUCNFLOCK1 is shown in Figure 3-58 and described in Table 3-52.

Return to the Summary Table.

Lock bit for MCUCNFx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-58 MCUCNFLOCK1 Register
3130292827262524
MCUCNF31RESERVEDMCUCNF26RESERVED
R/WSonce-0hR-0-0hR/WSonce-0hR-0-0h
2322212019181716
MCUCNF23RESERVEDMCUCNF19MCUCNF18MCUCNF17RESERVED
R/WSonce-0hR-0-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR-0-0h
15141312111098
RESERVEDMCUCNF10RESERVED
R-0-0hR/WSonce-0hR-0-0h
76543210
RESERVEDMCUCNF4RESERVEDMCUCNF2MCUCNF1RESERVED
R-0-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR-0-0h
Table 3-52 MCUCNFLOCK1 Register Field Descriptions
BitFieldTypeResetDescription
31MCUCNF31R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

30-27RESERVEDR-00hReserved
26MCUCNF26R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

25-24RESERVEDR-00hReserved
23MCUCNF23R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

22-20RESERVEDR-00hReserved
19MCUCNF19R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

18MCUCNF18R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

17MCUCNF17R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

16-11RESERVEDR-00hReserved
10MCUCNF10R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

9-5RESERVEDR-00hReserved
4MCUCNF4R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3RESERVEDR/WSonce0hReserved
2MCUCNF2R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

1MCUCNF1R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

0RESERVEDR-00hReserved

3.13.2.32 MCUCNFLOCK2 Register (Offset = 340h) [Reset = 00000000h]

MCUCNFLOCK2 is shown in Figure 3-59 and described in Table 3-53.

Return to the Summary Table.

Lock bit for MCUCNFx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-59 MCUCNFLOCK2 Register
313029282726252423222120191817161514131211109876543210
RESERVED
R/WSonce-0h
Table 3-53 MCUCNFLOCK2 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR/WSonce0hReserved

3.13.2.33 MCUCNFLOCK3 Register (Offset = 344h) [Reset = 00000000h]

MCUCNFLOCK3 is shown in Figure 3-60 and described in Table 3-54.

Return to the Summary Table.

Lock bit for MCUCNFx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-60 MCUCNFLOCK3 Register
3130292827262524
RESERVEDMCUCNF95RESERVED
R/WSonce-0hR/WSonce-0hR-0-0h
2322212019181716
RESERVEDMCUCNF81RESERVED
R-0-0hR/WSonce-0hR-0-0h
15141312111098
MCUCNF79MCUCNF78RESERVEDMCUCNF76RESERVEDMCUCNF74RESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR-0-0hR/WSonce-0hR-0-0hR/WSonce-0hR-0-0hR-0-0h
76543210
RESERVEDMCUCNF65MCUCNF64
R/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-54 MCUCNFLOCK3 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WSonce0hReserved
30MCUCNF95R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

29-18RESERVEDR-00hReserved
17MCUCNF81R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

16RESERVEDR-00hReserved
15MCUCNF79R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

14MCUCNF78R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

13RESERVEDR-00hReserved
12MCUCNF76R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

11RESERVEDR-00hReserved
10MCUCNF74R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

9RESERVEDR-00hReserved
8RESERVEDR-00hReserved
7-2RESERVEDR/WSonce0hReserved
1MCUCNF65R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

0MCUCNF64R/WSonce0hLock bit for MCUCNF register:
0: Register is not locked
1: Register is locked

Reset type: CPU1.SYSRSn

3.13.2.34 LSEN Register (Offset = 348h) [Reset = 00000001h]

LSEN is shown in Figure 3-61 and described in Table 3-55.

Return to the Summary Table.

Lockstep enable configuration

Figure 3-61 LSEN Register
3130292827262524
Rserved
R-0-0h
2322212019181716
Rserved
R-0-0h
15141312111098
Rserved
R-0-0h
76543210
RservedEnable
R-0-0hR/W-1h
Table 3-55 LSEN Register Field Descriptions
BitFieldTypeResetDescription
31-1RservedR-00hReserved

Reset type: PORESETn

0EnableR/W1h0: Lockstep is disabled
1: Lockstep is enabled
Note: User is expected to lock and commit the specific configuration as inadvertent clearing of the bit will cause lockstep to be disabled.

Reset type: PORESETn

3.13.2.35 EPWMXLINKCFG Register (Offset = 37Ch) [Reset = 00000000h]

EPWMXLINKCFG is shown in Figure 3-62 and described in Table 3-56.

Return to the Summary Table.

Configure which EPWM module instaces are linked in the XLINK scheme

Figure 3-62 EPWMXLINKCFG Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDEPWM18EPWM17
R-0-0hR/W-0hR/W-0h
15141312111098
EPWM16EPWM15EPWM14EPWM13EPWM12EPWM11EPWM10EPWM9
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EPWM8EPWM7EPWM6EPWM5EPWM4EPWM3EPWM2EPWM1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-56 EPWMXLINKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17EPWM18R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

16EPWM17R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

15EPWM16R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

14EPWM15R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

13EPWM14R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

12EPWM13R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

11EPWM12R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

10EPWM11R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

9EPWM10R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

8EPWM9R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

7EPWM8R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

6EPWM7R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

5EPWM6R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

4EPWM5R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

3EPWM4R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

2EPWM3R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

1EPWM2R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

0EPWM1R/W0hSelects Peripheral instance mirrored to the XLINK Region

0: Disabled - Module instance is not mirrored to XLINK
1: Enabled - Module instance is mirrored to XLINK

Reset type: CPU1.SYSRSn

3.13.2.36 SICCONFIG Register (Offset = 384h) [Reset = FFFF0000h]

SICCONFIG is shown in Figure 3-63 and described in Table 3-57.

Return to the Summary Table.

Safety Interconnect(SIC) Configuration - Enable and READY TIMEOUT value

Figure 3-63 SICCONFIG Register
3130292827262524
TIMEOUT
R/W-FFFFh
2322212019181716
TIMEOUT
R/W-FFFFh
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDEnable
R-0-0hR/W-0h
Table 3-57 SICCONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-16TIMEOUTR/WFFFFhSafety Interconnect (SIC) READY TIMEOUT value, in terms of number of clock cycles.

This is a 16-bit value common across multiple CPU, DMA or any other initiator on the inyterconnect. This value controls the input to the C29 CPU/SIC to detect bus-hang condition.

Due to a fault, if ready is pulled low by the endpoint longer than number of clock cycles programmed in this register, then timeout logic inside SIC will generate abort access to endpoint and aborts the ongoing access on bus, communicates as error on the error interface bus.

Reset type: XRSn

15-1RESERVEDR-00hReserved
0EnableR/W0hSafety Interconnect (SIC) Enable

Reset type: XRSn

3.13.2.37 RSTSTAT Register (Offset = 3B0h) [Reset = 00000000h]

RSTSTAT is shown in Figure 3-64 and described in Table 3-58.

Return to the Summary Table.

Reset Status register for secondary CPUs

Figure 3-64 RSTSTAT Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W1S-0hR/W1S-0hR/W1S-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDCPU3CPU2
R/W1S-0hR/W1S-0hR/W1S-0hR-0hR-0hR-0hR-0hR-0h
Table 3-58 RSTSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR-00hReserved
11-10RESERVEDR/W1S0hReserved
9RESERVEDR/W1S0hReserved
8RESERVEDR/W1S0hReserved
7RESERVEDR/W1S0hReserved
6RESERVEDR/W1S0hReserved
5RESERVEDR/W1S0hReserved
4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1CPU3R0hReset status of CPU3 to CPU1

0: CPU3 core is in reset
1: CPU3 core is out of reset

Reset type: CPU1.SYSRSn

0CPU2R0hReset status of CPU2 to CPU1

0: CPU2 core is in reset
1: CPU2 core is out of reset

Reset type: CPU1.SYSRSn

3.13.2.38 LPMSTAT Register (Offset = 3B4h) [Reset = 00000000h]

LPMSTAT is shown in Figure 3-65 and described in Table 3-59.

Return to the Summary Table.

LPM Status Register for secondary CPUs

Figure 3-65 LPMSTAT Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVEDCPU3CPU2
R-0-0hR-0hR-0hR-0hR-0hR-0h
Table 3-59 LPMSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR-00hReserved
9-8RESERVEDR0hReserved
7-6RESERVEDR0hReserved
5-4RESERVEDR0hReserved
3-2CPU3R0hThese bits indicate the power mode CPU3

00: CPU is in ACTIVE mode
01: CPU is in IDLE mode
10: CPU is in STANDBY mode
11: Reserved

Reset type: CPU1.SYSRSn

1-0CPU2R0hThese bits indicate the power mode CPU2

00: CPU is in ACTIVE mode
01: CPU is in IDLE mode
10: CPU is in STANDBY mode
11: Reserved

Reset type: CPU1.SYSRSn

3.13.2.39 TAP_STATUS Register (Offset = 3CCh) [Reset = 00000000h]

TAP_STATUS is shown in Figure 3-66 and described in Table 3-60.

Return to the Summary Table.

Status of JTAG State machine & Debugger Connect

Figure 3-66 TAP_STATUS Register
3130292827262524
DCONRESERVED
R-0hR-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
TAP_STATE
R-0h
76543210
TAP_STATE
R-0h
Table 3-60 TAP_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31DCONR0hDebugConnect indication from IcePick.

Reset type: PORESETn

30-16RESERVEDR-00hReserved
15-0TAP_STATER0hTAP State Vector. With bits representing, Connect coresponding POTAP* output to the
0:TLR,
1:IDLE,
2:SELECTDR,
3:CAPDR,
4:SHIFTDR,
5:EXIT1DR,
6:PAUSEDR,
7:EXIT2DR,
8:UPDTDR,
9:SLECTIR,
10:CAPIR,
11:SHIFTIR,
12:EXIT1IR,
13:PAUSEIR,
14:EXIT2IR,
15:UPDTIR,

Reset type: PORESETn

3.13.2.40 TAP_CONTROL Register (Offset = 3D0h) [Reset = 00000000h]

TAP_CONTROL is shown in Figure 3-67 and described in Table 3-61.

Return to the Summary Table.

Disable TAP control

Figure 3-67 TAP_CONTROL Register
3130292827262524
KEY
R-0/W-0h
2322212019181716
KEY
R-0/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDBSCAN_DIS
R-0-0hR/W-0h
Table 3-61 TAP_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hWrite to this register succeeds only if this field is written with a value of 0xa5a5

Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored

Reset type: PORESETn

15-1RESERVEDR-00hReserved
0BSCAN_DISR/W0hDisables BSCAN TAP control :

0: BSCAN TAP control enabled
1: BSCAN TAP control disabled

Reset type: PORESETn

3.13.2.41 DEVLIFECYCLE Register (Offset = 3D4h) [Reset = 00000000h]

DEVLIFECYCLE is shown in Figure 3-68 and described in Table 3-62.

Return to the Summary Table.

Reflect the state of the Device Life Cycle signals reported from the HSM

Figure 3-68 DEVLIFECYCLE Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDOVRNOFLASHOVRFLASH
R-0-0hR-0hR-0h
15141312111098
RESERVEDHSSUBTYPE
R-0-0hR-0h
76543210
RESERVEDDEVTYPE
R-0-0hR-0h
Table 3-62 DEVLIFECYCLE Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17OVRNOFLASHR0hTI Override mode with no access to Flash

Reset type: PORESETn

16OVRFLASHR0hTI Override mode with access to Flash

Reset type: PORESETn

15-12RESERVEDR-00hReserved
11-8HSSUBTYPER0hThese bits reflect the state of the signals from the HSM DEVICE_HS_SUBTYPE

Field values:
4'b1010: FS (Field Securable)
4'b0011: KP (Keys Provisioned)
4'b1111: FA (Failure Analysis)
Other: SE (Security Enforced)

Reset type: PORESETn

7-4RESERVEDR-00hReserved
3-0DEVTYPER0hThese bits reflect the state of the signals from the HSM DEVICE_TYPE

Field values:
4'b0101: TEST
4'b1001: EMU (EMULATOR)
4'b1010: HS (HIGH_SECURITY)
4'b0011: GP (GENERAL_PURPOSE)
Other: BAD

Reset type: PORESETn

3.13.2.42 SDFMTYPE Register (Offset = 47Ch) [Reset = 00000000h]

SDFMTYPE is shown in Figure 3-69 and described in Table 3-63.

Return to the Summary Table.

Based on the configuration enables disables features associated with the SDFM type.

Figure 3-69 SDFMTYPE Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
LOCKRESERVED
R/WSonce-0hR-0-0h
76543210
RESERVEDTYPE
R-0-0hR/W-0h
Table 3-63 SDFMTYPE Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15LOCKR/WSonce0h1: Write to this register is not allowed.
0: Write to this register is allowed.

Reset type: CPU1.SYSRSn

14-2RESERVEDR-00hReserved
1-0TYPER/W0h'00,10,11' :
1. Data Ready conditions combined with the fault conditions on the SDFM interrupt line.
2. Data ready interrupts from individual filters are not generated.
'01' :
1. Data Ready conditions do not generate the SDFMINT.
2. Each filter generates a separate data ready interrupts.

Reset type: CPU1.SYSRSn

3.13.2.43 SYNCSELECT Register (Offset = 4ACh) [Reset = 00000000h]

SYNCSELECT is shown in Figure 3-70 and described in Table 3-64.

Return to the Summary Table.

Sync Input and Output Select Register

Figure 3-70 SYNCSELECT Register
3130292827262524
RESERVEDSYNCOUT
R/W-0hR/W-0h
2322212019181716
RESERVEDRESERVED
R-0-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0h
Table 3-64 SYNCSELECT Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0hReserved
28-24SYNCOUTR/W0hSelect Syncout Source:

00000: EPWM1SYNCOUT selected to drive the SYNCOUT pin.
00001: EPWM2SYNCOUT selected to drive the SYNCOUT pin.
00010: EPWM3SYNCOUT selected to drive the SYNCOUT pin.
00011: EPWM4SYNCOUT selected to drive the SYNCOUT pin.
00100: EPWM5SYNCOUT selected to drive the SYNCOUT pin.
00101: EPWM6SYNCOUT selected to drive the SYNCOUT pin.
00110: EPWM7SYNCOUT selected to drive the SYNCOUT pin.
00111: EPWM8SYNCOUT selected to drive the SYNCOUT pin.
01000: EPWM9SYNCOUT selected to drive the SYNCOUT pin.
01001: EPWM10SYNCOUT selected to drive the SYNCOUT pin.
01010: EPWM11SYNCOUT selected to drive the SYNCOUT pin.
01011: EPWM12SYNCOUT selected to drive the SYNCOUT pin.
01100: EPWM13SYNCOUT selected to drive the SYNCOUT pin.
01101: EPWM14SYNCOUT selected to drive the SYNCOUT pin.
01110: EPWM15SYNCOUT selected to drive the SYNCOUT pin.
01111: EPWM16SYNCOUT selected to drive the SYNCOUT pin.
10000: EPWM17SYNCOUT selected to drive the SYNCOUT pin.
10001: EPWM18SYNCOUT selected to drive the SYNCOUT pin.
10010: Reserved
10011: Reserved
10100: Reserved
10101: Reserved
10110: Reserved
10111: Reserved
11000: ECAP1SYNCOUT selected to drive the SYNCOUT pin.
11001: ECAP2SYNCOUT selected to drive the SYNCOUT pin.
11010: ECAP3SYNCOUT selected to drive the SYNCOUT pin.
11011: ECAP4SYNCOUT selected to drive the SYNCOUT pin.
11100: ECAP5SYNCOUT selected to drive the SYNCOUT pin.
11101: ECAP6SYNCOUT selected to drive the SYNCOUT pin.
11110: Reserved.
11111: Reserved

Notes:
[1] Reserved position defaults to 00 selection

Reset type: CPU1.SYSRSn

23-18RESERVEDR-00hReserved
17-15RESERVEDR/W0hReserved
14-12RESERVEDR/W0hReserved
11-9RESERVEDR/W0hReserved
8-6RESERVEDR/W0hReserved
5-3RESERVEDR/W0hReserved
2-0RESERVEDR/W0hReserved

3.13.2.44 ADCSOCOUTSELECT Register (Offset = 4B0h) [Reset = 00000000h]

ADCSOCOUTSELECT is shown in Figure 3-71 and described in Table 3-65.

Return to the Summary Table.

External ADCSOC Select Register (PWM1-16)

Figure 3-71 ADCSOCOUTSELECT Register
3130292827262524
PWM16SOBAENPWM15SOBAENPWM14SOBAENPWM13SOCBENPWM12SOBAENPWM11SOBAENPWM10SOBAENPWM9SOCBEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
PWM8SOCBENPWM7SOCBENPWM6SOCBENPWM5SOCBENPWM4SOCBENPWM3SOCBENPWM2SOCBENPWM1SOCBEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
PWM16SOCAENPWM15SOCAENPWM14SOCAENPWM13SOCAENPWM12SOCAENPWM11SOCAENPWM10SOCAENPWM9SOCAEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
PWM8SOCAENPWM7SOCAENPWM6SOCAENPWM5SOCAENPWM4SOCAENPWM3SOCAENPWM2SOCAENPWM1SOCAEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-65 ADCSOCOUTSELECT Register Field Descriptions
BitFieldTypeResetDescription
31PWM16SOBAENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

30PWM15SOBAENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

29PWM14SOBAENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

28PWM13SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

27PWM12SOBAENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

26PWM11SOBAENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

25PWM10SOBAENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

24PWM9SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

23PWM8SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

22PWM7SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

21PWM6SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

20PWM5SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

19PWM4SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

18PWM3SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

17PWM2SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

16PWM1SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

15PWM16SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

14PWM15SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

13PWM14SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

12PWM13SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

11PWM12SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

10PWM11SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

9PWM10SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

8PWM9SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

7PWM8SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

6PWM7SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

5PWM6SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

4PWM5SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

3PWM4SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

2PWM3SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

1PWM2SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

0PWM1SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

3.13.2.45 ADCSOCOUTSELECT1 Register (Offset = 4B4h) [Reset = 00000000h]

ADCSOCOUTSELECT1 is shown in Figure 3-72 and described in Table 3-66.

Return to the Summary Table.

External ADCSOC Select Register (PWM17-32)

Figure 3-72 ADCSOCOUTSELECT1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDPWM18SOCBENPWM17SOCBEN
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWM18SOCAENPWM17SOCAEN
R-0-0hR/W-0hR/W-0h
Table 3-66 ADCSOCOUTSELECT1 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17PWM18SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

16PWM17SOCBENR/W0hADCSOCBOn source select:

0: Respective EPWM SOCB output is not selected
1: Respective EPWM SOCB output is selected

Reset type: CPU1.SYSRSn

15-2RESERVEDR-00hReserved
1PWM18SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

0PWM17SOCAENR/W0hADCSOCAOn source select:

0: Respective EPWM SOCA output is not selected
1: Respective EPWM SOCA output is selected

Reset type: CPU1.SYSRSn

3.13.2.46 SYNCSOCLOCK Register (Offset = 4B8h) [Reset = 00000000h]

SYNCSOCLOCK is shown in Figure 3-73 and described in Table 3-67.

Return to the Summary Table.

SYNCSEL and ADCSOC Select Lock register

Figure 3-73 SYNCSOCLOCK Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDADCSOCOUTSELECT1ADCSOCOUTSELECTSYNCSELECT
R-0-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-67 SYNCSOCLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR-00hReserved
2ADCSOCOUTSELECT1R/WSonce0hADCSOCOUTSELECT1 Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed

Reset type: CPU1.SYSRSn

1ADCSOCOUTSELECTR/WSonce0hADCSOCOUTSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed

Reset type: CPU1.SYSRSn

0SYNCSELECTR/WSonce0hSYNCSELECT Register Lock bit:
0: Respective register is not locked
1: Respective register is locked.
Notes:
[1] Any bit in this register, once set can only be creaed through a SYSRSn. Write of 0 to any bit of this regtister has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed

Reset type: CPU1.SYSRSn

3.13.2.47 HSMTOCPU_STS1 Register (Offset = 4DCh) [Reset = 00000000h]

HSMTOCPU_STS1 is shown in Figure 3-74 and described in Table 3-68.

Return to the Summary Table.

Communicate from HSM to CPU control signal

Figure 3-74 HSMTOCPU_STS1 Register
3130292827262524
SOC_GENR_2
R-0h
2322212019181716
SOC_GENR_1
R-0h
15141312111098
RESERVEDMPOSTLPOSTFLC2FLC1
R-0-0hR-0hR-0hR-0hR-0h
76543210
SRAM_BANK7SRAM_BANK6SRAM_BANK5SRAM_BANK4SRAM_BANK3SRAM_BANK2SRAM_BANK1SRAM_BANK0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 3-68 HSMTOCPU_STS1 Register Field Descriptions
BitFieldTypeResetDescription
31-24SOC_GENR_2R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

23-16SOC_GENR_1R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

15-12RESERVEDR-00hReserved
11MPOSTR0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

10LPOSTR0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

9FLC2R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

8FLC1R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

7SRAM_BANK7R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

6SRAM_BANK6R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

5SRAM_BANK5R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

4SRAM_BANK4R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

3SRAM_BANK3R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

2SRAM_BANK2R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

1SRAM_BANK1R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

0SRAM_BANK0R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

3.13.2.48 HSMTOCPU_STS2 Register (Offset = 4E0h) [Reset = 00000000h]

HSMTOCPU_STS2 is shown in Figure 3-75 and described in Table 3-69.

Return to the Summary Table.

Communicate from HSM to CPU control signal

Figure 3-75 HSMTOCPU_STS2 Register
3130292827262524
RESERVEDFLC2_BANK4
R-0-0hR-0h
2322212019181716
RESERVEDFLC1_BANK4FLC2_BANK3RESERVED
R-0-0hR-0hR-0hR-0-0h
15141312111098
FLC1_BANK3FLC2_BANK2RESERVEDFLC1_BANK2FLC2_BANK1RESERVED
R-0hR-0hR-0-0hR-0hR-0hR-0-0h
76543210
RESERVEDFLC1_BANK1FLC2_BANK0RESERVEDFLC1_BANK0
R-0-0hR-0hR-0hR-0-0hR-0h
Table 3-69 HSMTOCPU_STS2 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR-00hReserved
24FLC2_BANK4R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

23-21RESERVEDR-00hReserved
20FLC1_BANK4R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

19FLC2_BANK3R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

18-16RESERVEDR-00hReserved
15FLC1_BANK3R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

14FLC2_BANK2R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

13-11RESERVEDR-00hReserved
10FLC1_BANK2R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

9FLC2_BANK1R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

8-6RESERVEDR-00hReserved
5FLC1_BANK1R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

4FLC2_BANK0R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

3-1RESERVEDR-00hReserved
0FLC1_BANK0R0hRead-Only SIGNAL BIT for direct communication from HSM to CPU, to be used for handshake during Boot or Runtime

Reset type: CPU1.SYSRSn

3.13.2.49 HSM_SECURE_BOOT_INFO_REG0 Register (Offset = 4E4h) [Reset = 00000000h]

HSM_SECURE_BOOT_INFO_REG0 is shown in Figure 3-76 and described in Table 3-70.

Return to the Summary Table.

Communicate from HSM to CPU1 during secure Boot

Figure 3-76 HSM_SECURE_BOOT_INFO_REG0 Register
313029282726252423222120191817161514131211109876543210
STATUS
R-0h
Table 3-70 HSM_SECURE_BOOT_INFO_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR0hThese set of SW registers (HSM_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the HSM module to the SoC.

Reset type: PORESETn

3.13.2.50 HSM_SECURE_BOOT_INFO_REG1 Register (Offset = 4E8h) [Reset = 00000000h]

HSM_SECURE_BOOT_INFO_REG1 is shown in Figure 3-77 and described in Table 3-71.

Return to the Summary Table.

Communicate from HSM to CPU1 during secure Boot

Figure 3-77 HSM_SECURE_BOOT_INFO_REG1 Register
313029282726252423222120191817161514131211109876543210
STATUS
R-0h
Table 3-71 HSM_SECURE_BOOT_INFO_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR0hThese set of SW registers (HSM_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the HSM module to the SoC.

Reset type: PORESETn

3.13.2.51 HSM_SECURE_BOOT_INFO_REG2 Register (Offset = 4ECh) [Reset = 00000000h]

HSM_SECURE_BOOT_INFO_REG2 is shown in Figure 3-78 and described in Table 3-72.

Return to the Summary Table.

Communicate from HSM to CPU1 during secure Boot

Figure 3-78 HSM_SECURE_BOOT_INFO_REG2 Register
313029282726252423222120191817161514131211109876543210
STATUS
R-0h
Table 3-72 HSM_SECURE_BOOT_INFO_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR0hThese set of SW registers (HSM_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the HSM module to the SoC.

Reset type: PORESETn

3.13.2.52 HSM_SECURE_BOOT_INFO_REG3 Register (Offset = 4F0h) [Reset = 00000000h]

HSM_SECURE_BOOT_INFO_REG3 is shown in Figure 3-79 and described in Table 3-73.

Return to the Summary Table.

Communicate from HSM to CPU1 during secure Boot

Figure 3-79 HSM_SECURE_BOOT_INFO_REG3 Register
313029282726252423222120191817161514131211109876543210
STATUS
R-0h
Table 3-73 HSM_SECURE_BOOT_INFO_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR0hThese set of SW registers (HSM_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the HSM module to the SoC.

Reset type: PORESETn

3.13.2.53 HSM_SECURE_BOOT_INFO_REG4 Register (Offset = 4F4h) [Reset = 00000000h]

HSM_SECURE_BOOT_INFO_REG4 is shown in Figure 3-80 and described in Table 3-74.

Return to the Summary Table.

Communicate from HSM to CPU1 during secure Boot

Figure 3-80 HSM_SECURE_BOOT_INFO_REG4 Register
313029282726252423222120191817161514131211109876543210
STATUS
R-0h
Table 3-74 HSM_SECURE_BOOT_INFO_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR0hThese set of SW registers (HSM_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the HSM module to the SoC.

Reset type: PORESETn

3.13.2.54 HSM_SECURE_BOOT_INFO_REG5 Register (Offset = 4F8h) [Reset = 00000000h]

HSM_SECURE_BOOT_INFO_REG5 is shown in Figure 3-81 and described in Table 3-75.

Return to the Summary Table.

Communicate from HSM to CPU1 during secure Boot

Figure 3-81 HSM_SECURE_BOOT_INFO_REG5 Register
313029282726252423222120191817161514131211109876543210
STATUS
R-0h
Table 3-75 HSM_SECURE_BOOT_INFO_REG5 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR0hThese set of SW registers (HSM_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the HSM module to the SoC.

Reset type: PORESETn

3.13.2.55 HSM_SECURE_BOOT_INFO_REG6 Register (Offset = 4FCh) [Reset = 00000000h]

HSM_SECURE_BOOT_INFO_REG6 is shown in Figure 3-82 and described in Table 3-76.

Return to the Summary Table.

Communicate from HSM to CPU1 during secure Boot

Figure 3-82 HSM_SECURE_BOOT_INFO_REG6 Register
313029282726252423222120191817161514131211109876543210
STATUS
R-0h
Table 3-76 HSM_SECURE_BOOT_INFO_REG6 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR0hThese set of SW registers (HSM_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the HSM module to the SoC.

Reset type: PORESETn

3.13.2.56 HSM_SECURE_BOOT_INFO_REG7 Register (Offset = 500h) [Reset = 00000000h]

HSM_SECURE_BOOT_INFO_REG7 is shown in Figure 3-83 and described in Table 3-77.

Return to the Summary Table.

Communicate from HSM to CPU1 during secure Boot

Figure 3-83 HSM_SECURE_BOOT_INFO_REG7 Register
313029282726252423222120191817161514131211109876543210
STATUS
R-0h
Table 3-77 HSM_SECURE_BOOT_INFO_REG7 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR0hThese set of SW registers (HSM_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the HSM module to the SoC.

Reset type: PORESETn

3.13.2.57 SOC_SECURE_BOOT_INFO_REG0 Register (Offset = 504h) [Reset = 00000000h]

SOC_SECURE_BOOT_INFO_REG0 is shown in Figure 3-84 and described in Table 3-78.

Return to the Summary Table.

Communicate from CPU1 to HSM during secure Boot

Figure 3-84 SOC_SECURE_BOOT_INFO_REG0 Register
313029282726252423222120191817161514131211109876543210
STATUS
R/W-0h
Table 3-78 SOC_SECURE_BOOT_INFO_REG0 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR/W0hThese set of SW registers (SOC_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the SoC system control module to the HSM.

Reset type: PORESETn

3.13.2.58 SOC_SECURE_BOOT_INFO_REG1 Register (Offset = 508h) [Reset = 00000000h]

SOC_SECURE_BOOT_INFO_REG1 is shown in Figure 3-85 and described in Table 3-79.

Return to the Summary Table.

Communicate from CPU1 to HSM during secure Boot

Figure 3-85 SOC_SECURE_BOOT_INFO_REG1 Register
313029282726252423222120191817161514131211109876543210
STATUS
R/W-0h
Table 3-79 SOC_SECURE_BOOT_INFO_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR/W0hThese set of SW registers (SOC_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the SoC system control module to the HSM.

Reset type: PORESETn

3.13.2.59 SOC_SECURE_BOOT_INFO_REG2 Register (Offset = 50Ch) [Reset = 00000000h]

SOC_SECURE_BOOT_INFO_REG2 is shown in Figure 3-86 and described in Table 3-80.

Return to the Summary Table.

Communicate from CPU1 to HSM during secure Boot

Figure 3-86 SOC_SECURE_BOOT_INFO_REG2 Register
313029282726252423222120191817161514131211109876543210
STATUS
R/W-0h
Table 3-80 SOC_SECURE_BOOT_INFO_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR/W0hThese set of SW registers (SOC_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the SoC system control module to the HSM.

Reset type: PORESETn

3.13.2.60 SOC_SECURE_BOOT_INFO_REG3 Register (Offset = 510h) [Reset = 00000000h]

SOC_SECURE_BOOT_INFO_REG3 is shown in Figure 3-87 and described in Table 3-81.

Return to the Summary Table.

Communicate from CPU1 to HSM during secure Boot

Figure 3-87 SOC_SECURE_BOOT_INFO_REG3 Register
313029282726252423222120191817161514131211109876543210
STATUS
R/W-0h
Table 3-81 SOC_SECURE_BOOT_INFO_REG3 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR/W0hThese set of SW registers (SOC_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the SoC system control module to the HSM.

Reset type: PORESETn

3.13.2.61 SOC_SECURE_BOOT_INFO_REG4 Register (Offset = 514h) [Reset = 00000000h]

SOC_SECURE_BOOT_INFO_REG4 is shown in Figure 3-88 and described in Table 3-82.

Return to the Summary Table.

Communicate from CPU1 to HSM during secure Boot

Figure 3-88 SOC_SECURE_BOOT_INFO_REG4 Register
313029282726252423222120191817161514131211109876543210
STATUS
R/W-0h
Table 3-82 SOC_SECURE_BOOT_INFO_REG4 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR/W0hThese set of SW registers (SOC_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the SoC system control module to the HSM.

Reset type: PORESETn

3.13.2.62 SOC_SECURE_BOOT_INFO_REG5 Register (Offset = 518h) [Reset = 00000000h]

SOC_SECURE_BOOT_INFO_REG5 is shown in Figure 3-89 and described in Table 3-83.

Return to the Summary Table.

Communicate from CPU1 to HSM during secure Boot

Figure 3-89 SOC_SECURE_BOOT_INFO_REG5 Register
313029282726252423222120191817161514131211109876543210
STATUS
R/W-0h
Table 3-83 SOC_SECURE_BOOT_INFO_REG5 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR/W0hThese set of SW registers (SOC_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the SoC system control module to the HSM.

Reset type: PORESETn

3.13.2.63 SOC_SECURE_BOOT_INFO_REG6 Register (Offset = 51Ch) [Reset = 00000000h]

SOC_SECURE_BOOT_INFO_REG6 is shown in Figure 3-90 and described in Table 3-84.

Return to the Summary Table.

Communicate from CPU1 to HSM during secure Boot

Figure 3-90 SOC_SECURE_BOOT_INFO_REG6 Register
313029282726252423222120191817161514131211109876543210
STATUS
R/W-0h
Table 3-84 SOC_SECURE_BOOT_INFO_REG6 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR/W0hThese set of SW registers (SOC_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the SoC system control module to the HSM.

Reset type: PORESETn

3.13.2.64 SOC_SECURE_BOOT_INFO_REG7 Register (Offset = 520h) [Reset = 00000000h]

SOC_SECURE_BOOT_INFO_REG7 is shown in Figure 3-91 and described in Table 3-85.

Return to the Summary Table.

Communicate from CPU1 to HSM during secure Boot

Figure 3-91 SOC_SECURE_BOOT_INFO_REG7 Register
313029282726252423222120191817161514131211109876543210
STATUS
R/W-0h
Table 3-85 SOC_SECURE_BOOT_INFO_REG7 Register Field Descriptions
BitFieldTypeResetDescription
31-0STATUSR/W0hThese set of SW registers (SOC_SECURE_BOOT_INFO_REG0-7) hold the status information of the secure boot process for communication with the Host application. The definitions of the register fields (part of HSM_SOC_CTRL address space) are dependent on the implementation of the secure boot flow. These registers captures the output from the SoC system control module to the HSM.

Reset type: PORESETn

3.13.2.65 CLKCFGLOCK1 Register (Offset = 524h) [Reset = 00000000h]

CLKCFGLOCK1 is shown in Figure 3-92 and described in Table 3-86.

Return to the Summary Table.

Lock bit for CLKCFG registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed

Figure 3-92 CLKCFGLOCK1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDXCLKOUTDIVSELMCANCLKDIVSELHSMCLKDIVSELETHERCATCLKCTLEXTRFLTDETXTALCR
R-0-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
15141312111098
RESERVEDCLBCLKCTLPERCLKDIVSELRESERVEDSYSCLKDIVSELRESERVEDRESERVEDRESERVED
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
76543210
RESERVEDSYSPLLMULTRESERVEDRESERVEDSYSPLLCTL1CLKSRCCTL3CLKSRCCTL2CLKSRCCTL1
R/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0hR/WSonce-0h
Table 3-86 CLKCFGLOCK1 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR-00hReserved
21XCLKOUTDIVSELR/WSonce0hLock bit for XCLKOUTDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

20MCANCLKDIVSELR/WSonce0hLock bit for MCANCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

19HSMCLKDIVSELR/WSonce0hLock bit for HSMCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

18ETHERCATCLKCTLR/WSonce0hLock bit for ETHERCATCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

17EXTRFLTDETR/WSonce0hLock bit for EXTRFLTDET register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

16XTALCRR/WSonce0hCommon Lock bit for XTALCR & XTAL CR2 register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

15RESERVEDR/WSonce0hReserved
14CLBCLKCTLR/WSonce0hLock bit for CLBCLKCTL register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

13PERCLKDIVSELR/WSonce0hLock bit for PERCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

12RESERVEDR/WSonce0hReserved
11SYSCLKDIVSELR/WSonce0hLock bit for SYSCLKDIVSEL register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

10RESERVEDR/WSonce0hReserved
9RESERVEDR/WSonce0hReserved
8RESERVEDR/WSonce0hReserved
7RESERVEDR/WSonce0hReserved
6SYSPLLMULTR/WSonce0hLock bit for SYSPLLMULT register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

5RESERVEDR/WSonce0hReserved
4RESERVEDR/WSonce0hReserved
3SYSPLLCTL1R/WSonce0hLock bit for SYSPLLCTL1 register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

2CLKSRCCTL3R/WSonce0hLock bit for CLKSRCCTL3 register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

1CLKSRCCTL2R/WSonce0hLock bit for CLKSRCCTL2 register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

0CLKSRCCTL1R/WSonce0hLock bit for CLKSRCCTL1 register:
0: Respective register is not locked
1: Respective register is locked.

Reset type: CPU1.SYSRSn

3.13.2.66 CLKSRCCTL1 Register (Offset = 530h) [Reset = 00000000h]

CLKSRCCTL1 is shown in Figure 3-93 and described in Table 3-87.

Return to the Summary Table.

Clock Source Control register-1
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-93 CLKSRCCTL1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVED
R-0-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDOSCCLKSRCSEL
R/W-0hR-0-0hR/W-0hR/W-0hR/W-0hR-0-0hR/W-0h
Table 3-87 CLKSRCCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR-00hReserved
8RESERVEDR/W0hReserved
7RESERVEDR/W0hReserved
6RESERVEDR-00hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR-00hReserved
1-0OSCCLKSRCSELR/W0hOscillator Clock Source Select Bit: This bit selects the source for OSCCLK.
00 = INTOSC2 (default on reset)
01 = External Oscillator (XTAL)
10 = INTOSC1
11 = reserved (default to INTOSC1)

At power-up or after an XRSn, INTOSC2 is selected by default. Whenever the user changes the clock source using these bits, the SYSPLLMULT[13:0] register will be forced to zero and the PLL will be bypassed and powered down. This prevents potential PLL overshoot. The user will then have to write to the SYSPLLMULT register to configure the appropriate multiplier.
The user must wait 10 OSCCLK cycles before writing to SYSPLLMULT or disabling the previous clock source to allow the change to
complete..
Notes:
[1] INTOSC1 is recommended to be used only after missing clock detection. If user wants to re-lock the PLL with INTOSC1 (the back-up clock source) after missing clock is detected, he can do a MCLKCLR and lock the PLL.

Reset type: XRSn

3.13.2.67 CLKSRCCTL2 Register (Offset = 534h) [Reset = 00000000h]

CLKSRCCTL2 is shown in Figure 3-94 and described in Table 3-88.

Return to the Summary Table.

Clock Source Control register-2
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-94 CLKSRCCTL2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDMCANFBCLKSELMCANEBCLKSELMCANDBCLKSEL
R-0-0hR/W-0hR/W-0hR/W-0h
15141312111098
MCANCBCLKSELMCANBBCLKSELMCANABCLKSELRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
Table 3-88 CLKSRCCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR-00hReserved
21-20MCANFBCLKSELR/W0hMCAN Bit Clock Source Select Bit:
00 = PERx.SYSCLK
01 = AUXPLLRAWCLK (Reserved)
10 = AUXCLKIN
11 = PLLCLK
Missing clock detect circuit doesnt have any impact on these bits.

Reset type: XRSn

19-18MCANEBCLKSELR/W0hMCAN Bit Clock Source Select Bit:
00 = PERx.SYSCLK
01 = AUXPLLRAWCLK (Reserved)
10 = AUXCLKIN
11 = PLLCLK
Missing clock detect circuit doesnt have any impact on these bits.

Reset type: XRSn

17-16MCANDBCLKSELR/W0hMCAN Bit Clock Source Select Bit:
00 = PERx.SYSCLK
01 = AUXPLLRAWCLK (Reserved)
10 = AUXCLKIN
11 = PLLCLK
Missing clock detect circuit doesnt have any impact on these bits.

Reset type: XRSn

15-14MCANCBCLKSELR/W0hMCAN Bit Clock Source Select Bit:
00 = PERx.SYSCLK
01 = AUXPLLRAWCLK (Reserved)
10 = AUXCLKIN
11 = PLLCLK
Missing clock detect circuit doesnt have any impact on these bits.

Reset type: XRSn

13-12MCANBBCLKSELR/W0hMCAN Bit Clock Source Select Bit:
00 = PERx.SYSCLK
01 = AUXPLLRAWCLK (Reserved)
10 = AUXCLKIN
11 = PLLCLK
Missing clock detect circuit doesnt have any impact on these bits.

Reset type: XRSn

11-10MCANABCLKSELR/W0hMCAN Bit Clock Source Select Bit:
00 = PERx.SYSCLK
01 = AUXPLLRAWCLK (Reserved)
10 = AUXCLKIN
11 = PLLCLK
Missing clock detect circuit doesnt have any impact on these bits.

Reset type: XRSn

9-8RESERVEDR/W0hReserved
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

3.13.2.68 CLKSRCCTL3 Register (Offset = 538h) [Reset = 00000000h]

CLKSRCCTL3 is shown in Figure 3-95 and described in Table 3-89.

Return to the Summary Table.

Clock Source Control register-3
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-95 CLKSRCCTL3 Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDXCLKOUTSEL
R-0-0hR/W-0h
Table 3-89 CLKSRCCTL3 Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR-00hReserved
4-0XCLKOUTSELR/W0h00000 = PLLSYSCLK (default on reset)
00001 = CPU1.CLOCK
00010 = CPU2.CLOCK
00011 = CPU3.CLOCK
00100 = Reserved (AUXPLLCLK - After the Bypass Mux)
00101 = INTOSC1
00110 = INTOSC2
00111 = XTAL OSC o/p clock
01000 = Reserved (CMCLK)
01001 = PUMPOSC0 (from no-wrapper0)
01010 = SYSAPLL.CLK_AUX
01011 = Reserved (AUXAPLL.CLK_AUX)
01100 = Reserved (AUXPLLRAWCLK)
01101 = PUMPOSC1 (from FLC1)
01110 = PUMPOSC2 (from FLC2)
01111 = PLLRAWCLK
10000 = PLLCLK (After the Bypass Mux)
10001 = Reserved (CPU4.CLOCK)
10010 = Reserved (CPU5.CLOCK)
10011 = Reserved (CPU6.CLOCK)
10100 = Reserved
10101 = Reserved
10110 = Reserved
10111 = Reserved
11000 = Reserved
11001 = Reserved
11010 = Reserved
11011 = Reserved
11100 = Reserved

Reset type: XRSn

3.13.2.69 SYSPLLCTL1 Register (Offset = 53Ch) [Reset = 00000000h]

SYSPLLCTL1 is shown in Figure 3-96 and described in Table 3-90.

Return to the Summary Table.

SYSPLL Control register-1
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-96 SYSPLLCTL1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDPLLCLKENPLLEN
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-90 SYSPLLCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1PLLCLKENR/W0hSYSPLL bypassed or included in the PLLSYSCLK path: This bit decides if the SYSPLL is bypassed when PLLSYSCLK is generated

1 = PLLSYSCLK is fed from the SYSPLL clock output. Users need to make sure that the PLL is locked before enabling this clock to the system.
0 = SYSPLL is bypassed. Clock to system is direct feed from OSCCLK

Reset type: XRSn

0PLLENR/W0hSYSPLL enabled or disabled: This bit decides if the SYSPLL is enabled or not

1 = SYSPLL is enabled
0 = SYSPLL is powered off. Clock to system is direct feed from OSCCLK

Reset type: XRSn

3.13.2.70 SYSPLLMULT Register (Offset = 548h) [Reset = 00000000h]

SYSPLLMULT is shown in Figure 3-97 and described in Table 3-91.

Return to the Summary Table.

SYSPLL Multiplier register

NOTE: FMULT and IMULT fields must be written at the same time for correct PLL operation.
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-97 SYSPLLMULT Register
3130292827262524
RESERVEDREFDIV
R-0-0hR/W-0h
2322212019181716
RESERVEDODIV
R-0-0hR/W-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR-0-0hR/W-0h
76543210
IMULT
R/W-0h
Table 3-91 SYSPLLMULT Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR-00hReserved
28-24REFDIVR/W0hSYSPLL Reference Clock Divider

PLL Reference Divider = REFDIV + 1

Reset type: XRSn

23-21RESERVEDR-00hReserved
20-16ODIVR/W0hSYSPLL Output Clock Divider

PLL Output Divider = ODIV + 1

Reset type: XRSn

15-14RESERVEDR-00hReserved
13-12RESERVEDR/W0hReserved
11-10RESERVEDR-00hReserved
9-8RESERVEDR/W0hReserved
7-0IMULTR/W0hSYSPLL Integer Multiplier:
For 00000000 Fout = Fref (PLLBYPASS) Integer Multiplier = 1
00000001 Integer Multiplier = 1
00000010 Integer Multiplier = 2
00000011 Integer Multiplier = 3
.......
01111111 Integer Multipler = 127
.......
11111111 Integer Multipler = 255
Note for APLL Multiplier values from 0-3 are invalid, internally those will be treated to 4.

Reset type: XRSn

3.13.2.71 SYSPLLSTS Register (Offset = 54Ch) [Reset = 00000030h]

SYSPLLSTS is shown in Figure 3-98 and described in Table 3-92.

Return to the Summary Table.

SYSPLL Status register

Figure 3-98 SYSPLLSTS Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDSLIPS_NOTSUPPORTEDLOCKS
R-0-0hR-1hR-1hW1C-0hR-0hR-0hR-0h
Table 3-92 SYSPLLSTS Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR-00hReserved
5RESERVEDR1hReserved
4RESERVEDR1hReserved
3RESERVEDW1C0hReserved
2RESERVEDR0hReserved
1SLIPS_NOTSUPPORTEDR0hRESERVED: This bit is reserved and the value read should be ignored. TI recommends using DCC to evaluate SYSPLL Slip status.

Refer to InitSysPll() or SysCtl_setClock() functions inside the latest example software from C2000Ware for checking SYSPLL Slip status using DCC.

Reset type: XRSn

0LOCKSR0hSYSPLL Lock Status Bit: This bit indicates whether the SYSPLL is locked or not

0 = SYSPLL is not yet locked
1 = SYSPLL is locked

Reset type: XRSn

3.13.2.72 SYSCLKDIVSEL Register (Offset = 564h) [Reset = 00000000h]

SYSCLKDIVSEL is shown in Figure 3-99 and described in Table 3-93.

Return to the Summary Table.

System Clock Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-99 SYSCLKDIVSEL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVED
R-0-0hR/W-0h
76543210
RESERVEDPLLSYSCLKDIV
R-0-0hR/W-0h
Table 3-93 SYSCLKDIVSEL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR-00hReserved
8RESERVEDR/W0hReserved
7-6RESERVEDR-00hReserved
5-0PLLSYSCLKDIVR/W0hPLLSYSCLK Divide Select: This bit selects the divider setting for the PLLSYSCLK.

000000 = /1 (Default)
000001 = /2
000010 = /3
000011 = /4
000100 = /5
......
111111 = /64

Reset type: XRSn

3.13.2.73 PERCLKDIVSEL Register (Offset = 56Ch) [Reset = 00000911h]

PERCLKDIVSEL is shown in Figure 3-100 and described in Table 3-94.

Return to the Summary Table.

Peripheral Clock Divider Select register

Figure 3-100 PERCLKDIVSEL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDLINBCLKDIVRESERVEDLINACLKDIV
R-0-0hR/W-1hR-0-0hR/W-1h
76543210
RESERVEDRESERVEDEMIF1CLKDIVRESERVEDEPWMCLKDIV
R-0-0hR/W-0hR/W-1hR/W-0hR/W-1h
Table 3-94 PERCLKDIVSEL Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR-00hReserved
12-11LINBCLKDIVR/W1hLINB Clock Divide Select: This bit selects whether the LINB module run with a /1 or /2 clock.

00: /1 of SYSCLK is selected
01: /2 of SYSCLK is selected
10: /4 of SYSCLK is selected
11: Reserved

Reset type: CPU1.SYSRSn

10RESERVEDR-00hReserved
9-8LINACLKDIVR/W1hLINA Clock Divide Select: This bit selects whether the LINA module run with a /1 or /2 clock.

00: /1 of SYSCLK is selected
01: /2 of SYSCLK is selected
10: /4 of SYSCLK is selected
11: Reserved

Reset type: CPU1.SYSRSn

7RESERVEDR-00hReserved
6RESERVEDR/W0hReserved
5-4EMIF1CLKDIVR/W1hEMIF1 Clock Divide Select: This bit selects whether the EMIF1 module run with a /1 /2, or /4 clock.

For Dual core device
0: /1 of PLLSYSCLK is selected
1: /2 of PLLSYSCLK is selected
2: /4 of PLLSYSCLK is selected
3: Reserved

Reset type: CPU1.SYSRSn

3-2RESERVEDR/W0hReserved
1-0EPWMCLKDIVR/W1hEPWM Clock Divide Select: This bit selects whether the EPWM modules run with a /1 or /2 clock. This divider sits in front of the PLLSYSCLK

x0 = /1 of SYSCLK
x1 = /2 of SYSLCK

Note: Refer to the EPWM User Guide for maximum EPWM Frequency

Reset type: CPU1.SYSRSn

3.13.2.74 XCLKOUTDIVSEL Register (Offset = 570h) [Reset = 00000003h]

XCLKOUTDIVSEL is shown in Figure 3-101 and described in Table 3-95.

Return to the Summary Table.

XCLKOUT Divider Select register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-101 XCLKOUTDIVSEL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDXCLKOUTDIV
R-0-0hR/W-3h
Table 3-95 XCLKOUTDIVSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1-0XCLKOUTDIVR/W3hXCLKOUT Divide Select: This bit selects the divider setting for the XCLKOUT.

00 = /1
01 = /2
10 = /4
11 = /8 (default on reset)

Reset type: CPU1.SYSRSn

3.13.2.75 HSMCLKDIVSEL Register (Offset = 574h) [Reset = 00000001h]

HSMCLKDIVSEL is shown in Figure 3-102 and described in Table 3-96.

Return to the Summary Table.

HSM SYSCLK Divider Select register

Figure 3-102 HSMCLKDIVSEL Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
RESERVEDHSMCLKDIV
R-0-0hR/W-1h
Table 3-96 HSMCLKDIVSEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR-00hReserved
4-0HSMCLKDIVR/W1h00001 = /2
00010 = /4
...
Rest = Should be treated as value 00001=/2

Reset type: XRSn

3.13.2.76 MCANCLKDIVSEL Register (Offset = 578h) [Reset = 2739CE73h]

MCANCLKDIVSEL is shown in Figure 3-103 and described in Table 3-97.

Return to the Summary Table.

MCAN Bit Clock Divider Select register

Figure 3-103 MCANCLKDIVSEL Register
3130292827262524
RESERVEDMCANFCLKDIVMCANECLKDIV
R-0-0hR/W-13hR/W-13h
2322212019181716
MCANECLKDIVMCANDCLKDIV
R/W-13hR/W-13h
15141312111098
MCANDCLKDIVMCANCCLKDIVMCANBCLKDIV
R/W-13hR/W-13hR/W-13h
76543210
MCANBCLKDIVMCANACLKDIV
R/W-13hR/W-13h
Table 3-97 MCANCLKDIVSEL Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR-00hReserved
29-25MCANFCLKDIVR/W13h00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd

Reset type: XRSn

24-20MCANECLKDIVR/W13h00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd

Reset type: XRSn

19-15MCANDCLKDIVR/W13h00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd

Reset type: XRSn

14-10MCANCCLKDIVR/W13h00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd

Reset type: XRSn

9-5MCANBCLKDIVR/W13h00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd

Reset type: XRSn

4-0MCANACLKDIVR/W13h00000 = /1
00001 = /2
...
10010 = /19
10011 = /20
101xx = Rsvd
11xxx = Rsvd

Reset type: XRSn

3.13.2.77 CLBCLKCTL Register (Offset = 57Ch) [Reset = 00000007h]

CLBCLKCTL is shown in Figure 3-104 and described in Table 3-98.

Return to the Summary Table.

CLB Clocking Control Register

Figure 3-104 CLBCLKCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDCLKMODECLB6CLKMODECLB5CLKMODECLB4CLKMODECLB3CLKMODECLB2CLKMODECLB1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR-0-0hR/W-7h
Table 3-98 CLBCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR-00hReserved
23RESERVEDR/W0hReserved
22RESERVEDR/W0hReserved
21CLKMODECLB6R/W0h0 : CLB6 is synchronous to SYSCLK
1 : CLB6 runs of asynchronous clock

Reset type: SYSRSn

20CLKMODECLB5R/W0h0 : CLB5 is synchronous to SYSCLK
1 : CLB5 runs of asynchronous clock

Reset type: SYSRSn

19CLKMODECLB4R/W0h0 : CLB4 is synchronous to SYSCLK
1 : CLB4 runs of asynchronous clock

Reset type: SYSRSn

18CLKMODECLB3R/W0h0 : CLB3 is synchronous to SYSCLK
1 : CLB3 runs of asynchronous clock

Reset type: SYSRSn

17CLKMODECLB2R/W0h0 : CLB2 is synchronous to SYSCLK
1 : CLB2 runs of asynchronous clock

Reset type: SYSRSn

16CLKMODECLB1R/W0h0 : CLB1 is synchronous to SYSCLK
1 : CLB1 runs of asynchronous clock

Reset type: SYSRSn

15-5RESERVEDR-00hReserved
4RESERVEDR/W0hReserved
3RESERVEDR-00hReserved
2-0RESERVEDR/W7hReserved

3.13.2.78 MCDCR Register (Offset = 584h) [Reset = 00000000h]

MCDCR is shown in Figure 3-105 and described in Table 3-99.

Return to the Summary Table.

Missing Clock Detect Control Register

Figure 3-105 MCDCR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDEXTR_FAULT_MCD_ENEXTR_FAULTSCLREXTR_FAULTSRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR-0/W1S-0hR-0hR/W-0hR-0/W1S-0h
76543210
RESERVEDSYSREF_LOST_MCD_ENSYSREF_LOSTSCLRSYSREF_LOSTSOSCOFFMCLKOFFMCLKCLRMCLKSTS
R-0hR/W-0hR-0/W1S-0hR-0hR/W-0hR/W-0hR-0/W1S-0hR-0h
Table 3-99 MCDCR Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR-00hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12EXTR_FAULT_MCD_ENR/W0hControl to add 'EXTR FAULTt' as cause for MCD
0 = 'EXTR FAULT' does not affect MCD.
1 = Upon 'EXTR FAULT' MCD is asserted.

Reset type: XRSn

11EXTR_FAULTSCLRR-0/W1S0hClears the EXTR_FAULTS from MCDCR which is root for MCD trigger.
0 = No effect on present state of the EXTR_FAULTS
1 = Clears the EXTR_FAULTS bit to '0'. Bit clears itself after clear pulse to EXTR_FAULTS.
Read always gives '0'.

Reset type: XRSn

10EXTR_FAULTSR0hExternal Resistor fault status Bit: This bit indicates whether there is a critical fault in the external resistor connected to the device

0 = 'EXTR fault' event has not occurred.
1 = 'EXTR fault' event has occurred.

Reset type: XRSn

9RESERVEDR/W0hReserved
8RESERVEDR-0/W1S0hReserved
7RESERVEDR0hReserved
6SYSREF_LOST_MCD_ENR/W0hControl to add 'PLL reference clock lost' as cause for MCD
0 = 'PLL reference clock Lost' does not affect MCD.
1 = Upon 'PLL reference clock Lost' MCD is asserted.

Reset type: XRSn

5SYSREF_LOSTSCLRR-0/W1S0hClears the REF_LOST_STS from PLLSTS which is root for MCD trigger.
0 = No effect on present state of the REF_LOST_STS
1 = Clears the REF_LOST_STS bit to '0'. Bit clears itself after clear pulse to REF_LOST_STS.
Read always gives '0'.

Reset type: XRSn

4SYSREF_LOSTSR0hSYSPLL 'Reference Lost' Status Bit: This bit indicates whether the SYSPLL is out of lock range

0 = 'Reference Lost' event has not occurred.
1 = 'Reference Lost' event has occurred.

Reset type: XRSn

3OSCOFFR/W0hOscillator Clock Disconnect from MCD Bit:
0 = OSCCLK Connected to OSCCLK Counter in MCD module
1 = OSCCLK Disconnected to OSCCLK Counter in MCD module

Reset type: XRSn

2MCLKOFFR/W0hMissing Clock Detect Off Bit:
0 = Missing Clock Detect Circuit Enabled
1 = Missing Clock Detect Circuit Disabled

Reset type: XRSn

1MCLKCLRR-0/W1S0hMissing Clock Clear Bit:
Write 1' to this bit to clear MCLKSTS bit and reset the missing clock detect circuit.'

Reset type: XRSn

0MCLKSTSR0hMissing Clock Status Bit:
0 = OSCCLK Is OK
1 = OSCCLK Detected Missing, CLOCKFAILn Generated

Reset type: XRSn

3.13.2.79 X1CNT Register (Offset = 588h) [Reset = 00000000h]

X1CNT is shown in Figure 3-106 and described in Table 3-100.

Return to the Summary Table.

10-bit Counter on X1 Clock

Figure 3-106 X1CNT Register
31302928272625242322212019181716
RESERVEDCLR
R-0-0hR-0/W1C-0h
1514131211109876543210
RESERVEDX1CNT
R-0-0hR-0h
Table 3-100 X1CNT Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR-00hReserved
16CLRR-0/W1C0hX1 Counter clear:
A write of '1' to this bit field clears the X1CNT and makes it count from 0x0 again (provided X1 clock is ticking).
Writes of '0' are ignore to this bit field

Reset type: XRSn

15-11RESERVEDR-00hReserved
10-0X1CNTR0hX1 Counter:
- This counter increments on every X1 CLOCKs positive-edge.
- Once it reaches the values of 0x7ff, it freezes
- Before switching from INTOSC2 to X1, application must check this counter and make sure that it has saturated. This will ensure that the Crystal connected to X1/X2 is oscillating.

Reset type: XRSn

3.13.2.80 XTALCR Register (Offset = 58Ch) [Reset = 00000001h]

XTALCR is shown in Figure 3-107 and described in Table 3-101.

Return to the Summary Table.

XTAL Control Register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.

Figure 3-107 XTALCR Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDSEOSCOFF
R-0-0hR/W-0hR/W-0hR/W-1h
Table 3-101 XTALCR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR-00hReserved
2RESERVEDR/W0hReserved
1SER/W0hConfigures XTAL oscillator in single-ended or Crystal mode when
XTAL oscillator is powered up(i.e. OSCOFF = 0)

0 XTAL oscillator in Crystal mode
1 XTAL oscilator in single-ended mode (through X1)

Reset type: XRSn

0OSCOFFR/W1hThis bit if '1', powers-down the XTAL oscillator macro and hence doesn't let X2 to be driven by the XTAL oscillator. If a crystal is connected to X1/X2, user needs to first clear this bit, wait for the oscillator to power up (using X1CNT) and then only switch the clock source to X1/X2

Reset type: XRSn

3.13.2.81 XTALCR2 Register (Offset = 59Ch) [Reset = 00000003h]

XTALCR2 is shown in Figure 3-108 and described in Table 3-102.

Return to the Summary Table.

XTAL Control Register for pad init

Figure 3-108 XTALCR2 Register
31302928272625242322212019181716
RESERVED
R/W-0h
1514131211109876543210
RESERVEDFENXOFXIF
R-0-0hR/W-0hR/W-1hR/W-1h
Table 3-102 XTALCR2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0hReserved
15-3RESERVEDR-00hReserved
2FENR/W0hConfigures XTAL oscillator pad initilisation.
0 : XOSC pads are not driven through GPIO connection.
1 : XOSC pads are driven through connected GPIO as per XIF & XOF values.

This register has effect only when XOSC is OFF (no SE , no XTAL mode).
If this register is set during XOSC off state (XOSCOFF=1 & SE=0)
then upon change of these controls this bit gets reset and rearmed.

Reset type: XRSn

1XOFR/W1hPolarity selection to initialise XO /X2 pad of the XOSC before start-up
This value shall be deposited on the pad before XOSC started (XOSCOFF=1)
If FEN=0 or XOSC is in XTAL or SE mode
then this value will not be applied to the pad.

Reset type: XRSn

0XIFR/W1hPolarity selection to initialise XI /X1 pad of the XOSC before start-up
This value shall be deposited on the pad before XOSC started (XOSCOFF=1)
If FEN=0 or XOSC is in XTAL or SE mode
then this value will not be applied to the pad.

Reset type: XRSn

3.13.2.82 ETHERCATCLKCTL Register (Offset = 5A8h) [Reset = 0000000Eh]

ETHERCATCLKCTL is shown in Figure 3-109 and described in Table 3-103.

Return to the Summary Table.

EtherCAT Clock Control

Figure 3-109 ETHERCATCLKCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDPHYCLKEN
R-0hR/W-0h
76543210
RESERVEDECATDIVRESERVED
R-0-0hR/W-7hR/W-0h
Table 3-103 ETHERCATCLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8PHYCLKENR/W0h0 : etherCAT phy clock disabled
1 : etherCAT phy clock enabled

Reset type: XRSn

7-4RESERVEDR-00hReserved
3-1ECATDIVR/W7h000: /1
001: /2
010: /3
011: /4
100: /5
101: /6
110: /7
111: /8

Reset type: XRSn

0RESERVEDR/W0hReserved

3.13.2.83 ETHERCATCTL Register (Offset = 5ACh) [Reset = 00000000h]

ETHERCATCTL is shown in Figure 3-110 and described in Table 3-104.

Return to the Summary Table.

ETHERCAT control register.

Figure 3-110 ETHERCATCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDI2CLOOPBACK
R-0-0hR/W-0h
Table 3-104 ETHERCATCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0I2CLOOPBACKR/W0hETHERCAT I2C loopback enable Bit:

0: I2C port of etherCAT is not looped back to I2C_A
1: I2C port of etherCAT is looped back to I2C_A

Reset type: XRSn

3.13.2.84 SYNCBUSY Register (Offset = 5B0h) [Reset = 00000000h]

SYNCBUSY is shown in Figure 3-111 and described in Table 3-105.

Return to the Summary Table.

Pulse Transfer Sync Busy Status register

Figure 3-111 SYNCBUSY Register
3130292827262524
CPU2TMR2CTLCPU1TMR2CTLCPU3TMR2CTLCLKSRCCTL3CLKSRCCTL2CLKSRCCTL1XTALCRXCLKOUTDIVSEL
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
2322212019181716
SYSPLLMULTSYSPLLCTL1SYSCLKDIVSELPERCLKDIVSELETHERCATCLKCTLCLBCLKCTLRESERVEDMCANCLKDIVSEL
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDBUSY
R-0-0hR-0h
Table 3-105 SYNCBUSY Register Field Descriptions
BitFieldTypeResetDescription
31CPU2TMR2CTLR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

30CPU1TMR2CTLR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

29CPU3TMR2CTLR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

28CLKSRCCTL3R0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

27CLKSRCCTL2R0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

26CLKSRCCTL1R0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

25XTALCRR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

24XCLKOUTDIVSELR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

23SYSPLLMULTR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

22SYSPLLCTL1R0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

21SYSCLKDIVSELR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

20PERCLKDIVSELR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

19ETHERCATCLKCTLR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

18CLBCLKCTLR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

17RESERVEDR0hReserved
16MCANCLKDIVSELR0hThis status bit indicates write to the register is in progress
0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

15-1RESERVEDR-00hReserved
0BUSYR0hThis status bit indicates write to any of the following registers (OR_REDUCE) is in progress or not.

MCANCLKDIVSEL,CLBCLKCTL,ETHERCATCLKCTL,PERCLKDIVSEL,SYSCLKDIVSEL,SYSPLLCTL1,SYSPLLMULT,XCLKOUTDIVSEL,XTALCR,CLKSRCCTL1,CLKSRCCTL2,CLKSRCCTL3,CPU3TMR2CTL,CPU1TMR2CTL,CPU2TMR2CTL

0 : Not BUSY - No synchronization in progress
1 : BUSY - Synchronization is in progress

Reset type: SYSRSn

3.13.2.85 ESMXRSNCTL Register (Offset = 5C0h) [Reset = 00010001h]

ESMXRSNCTL is shown in Figure 3-112 and described in Table 3-106.

Return to the Summary Table.

Enable ESM reset outputs for XRSn

Figure 3-112 ESMXRSNCTL Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDESMRESET
R-0-0hR/W-1h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDESMCPU3HIPRIWDESMCPU3CRITICALESMCPU2HIPRIWDESMCPU2CRITICALRESERVEDESMCPU1CRITICAL
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
Table 3-106 ESMXRSNCTL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR-00hReserved
16ESMRESETR/W1hIf this bit is set, ESM output will be enabled to cause respective reset

Reset type: PORESETn

15-6RESERVEDR-00hReserved
5ESMCPU3HIPRIWDR/W0hIf this bit is set, ESM output will be enabled to cause XRSN

Reset type: PORESETn

4ESMCPU3CRITICALR/W0hIf this bit is set, ESM output will be enabled to cause XRSN

Reset type: PORESETn

3ESMCPU2HIPRIWDR/W0hIf this bit is set, ESM output will be enabled to cause XRSN

Reset type: PORESETn

2ESMCPU2CRITICALR/W0hIf this bit is set, ESM output will be enabled to cause XRSN

Reset type: PORESETn

1RESERVEDR/W0hReserved
0ESMCPU1CRITICALR/W1hIf this bit is set, respective ESM output will be enabled to cause XRSN

Reset type: PORESETn

3.13.2.86 EPWM1 Register (Offset = 5C8h) [Reset = 000000C0h]

EPWM1 is shown in Figure 3-113 and described in Table 3-107.

Return to the Summary Table.

PER2SYSCONFIG - Peripheral System Configuration for EPWM1

Figure 3-113 EPWM1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-107 EPWM1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.87 EPWM2 Register (Offset = 5CCh) [Reset = 000000C0h]

EPWM2 is shown in Figure 3-114 and described in Table 3-108.

Return to the Summary Table.

PER3SYSCONFIG - Peripheral System Configuration for EPWM2

Figure 3-114 EPWM2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-108 EPWM2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.88 EPWM3 Register (Offset = 5D0h) [Reset = 000000C0h]

EPWM3 is shown in Figure 3-115 and described in Table 3-109.

Return to the Summary Table.

PER4SYSCONFIG - Peripheral System Configuration for EPWM3

Figure 3-115 EPWM3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-109 EPWM3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.89 EPWM4 Register (Offset = 5D4h) [Reset = 000000C0h]

EPWM4 is shown in Figure 3-116 and described in Table 3-110.

Return to the Summary Table.

PER5SYSCONFIG - Peripheral System Configuration for EPWM4

Figure 3-116 EPWM4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-110 EPWM4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.90 EPWM5 Register (Offset = 5D8h) [Reset = 000000C0h]

EPWM5 is shown in Figure 3-117 and described in Table 3-111.

Return to the Summary Table.

PER6SYSCONFIG - Peripheral System Configuration for EPWM5

Figure 3-117 EPWM5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-111 EPWM5 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.91 EPWM6 Register (Offset = 5DCh) [Reset = 000000C0h]

EPWM6 is shown in Figure 3-118 and described in Table 3-112.

Return to the Summary Table.

PER7SYSCONFIG - Peripheral System Configuration for EPWM6

Figure 3-118 EPWM6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-112 EPWM6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.92 EPWM7 Register (Offset = 5E0h) [Reset = 000000C0h]

EPWM7 is shown in Figure 3-119 and described in Table 3-113.

Return to the Summary Table.

PER8SYSCONFIG - Peripheral System Configuration for EPWM7

Figure 3-119 EPWM7 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-113 EPWM7 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.93 EPWM8 Register (Offset = 5E4h) [Reset = 000000C0h]

EPWM8 is shown in Figure 3-120 and described in Table 3-114.

Return to the Summary Table.

PER9SYSCONFIG - Peripheral System Configuration for EPWM8

Figure 3-120 EPWM8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-114 EPWM8 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.94 EPWM9 Register (Offset = 5E8h) [Reset = 000000C0h]

EPWM9 is shown in Figure 3-121 and described in Table 3-115.

Return to the Summary Table.

PER10SYSCONFIG - Peripheral System Configuration for EPWM9

Figure 3-121 EPWM9 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-115 EPWM9 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.95 EPWM10 Register (Offset = 5ECh) [Reset = 000000C0h]

EPWM10 is shown in Figure 3-122 and described in Table 3-116.

Return to the Summary Table.

PER11SYSCONFIG - Peripheral System Configuration for EPWM10

Figure 3-122 EPWM10 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-116 EPWM10 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.96 EPWM11 Register (Offset = 5F0h) [Reset = 000000C0h]

EPWM11 is shown in Figure 3-123 and described in Table 3-117.

Return to the Summary Table.

PER12SYSCONFIG - Peripheral System Configuration for EPWM11

Figure 3-123 EPWM11 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-117 EPWM11 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.97 EPWM12 Register (Offset = 5F4h) [Reset = 000000C0h]

EPWM12 is shown in Figure 3-124 and described in Table 3-118.

Return to the Summary Table.

PER13SYSCONFIG - Peripheral System Configuration for EPWM12

Figure 3-124 EPWM12 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-118 EPWM12 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.98 EPWM13 Register (Offset = 5F8h) [Reset = 000000C0h]

EPWM13 is shown in Figure 3-125 and described in Table 3-119.

Return to the Summary Table.

PER14SYSCONFIG - Peripheral System Configuration for EPWM13

Figure 3-125 EPWM13 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-119 EPWM13 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.99 EPWM14 Register (Offset = 5FCh) [Reset = 000000C0h]

EPWM14 is shown in Figure 3-126 and described in Table 3-120.

Return to the Summary Table.

PER15SYSCONFIG - Peripheral System Configuration for EPWM14

Figure 3-126 EPWM14 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-120 EPWM14 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.100 EPWM15 Register (Offset = 600h) [Reset = 000000C0h]

EPWM15 is shown in Figure 3-127 and described in Table 3-121.

Return to the Summary Table.

PER16SYSCONFIG - Peripheral System Configuration for EPWM15

Figure 3-127 EPWM15 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-121 EPWM15 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.101 EPWM16 Register (Offset = 604h) [Reset = 000000C0h]

EPWM16 is shown in Figure 3-128 and described in Table 3-122.

Return to the Summary Table.

PER17SYSCONFIG - Peripheral System Configuration for EPWM16

Figure 3-128 EPWM16 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-122 EPWM16 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.102 EPWM17 Register (Offset = 608h) [Reset = 000000C0h]

EPWM17 is shown in Figure 3-129 and described in Table 3-123.

Return to the Summary Table.

PER18SYSCONFIG - Peripheral System Configuration for EPWM17

Figure 3-129 EPWM17 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-123 EPWM17 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.103 EPWM18 Register (Offset = 60Ch) [Reset = 000000C0h]

EPWM18 is shown in Figure 3-130 and described in Table 3-124.

Return to the Summary Table.

PER19SYSCONFIG - Peripheral System Configuration for EPWM18

Figure 3-130 EPWM18 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-124 EPWM18 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.104 HRCAL0 Register (Offset = 614h) [Reset = 000000C0h]

HRCAL0 is shown in Figure 3-131 and described in Table 3-125.

Return to the Summary Table.

PER21SYSCONFIG - Peripheral System Configuration for HRCAL0

Figure 3-131 HRCAL0 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-125 HRCAL0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.105 HRCAL1 Register (Offset = 618h) [Reset = 000000C0h]

HRCAL1 is shown in Figure 3-132 and described in Table 3-126.

Return to the Summary Table.

PER22SYSCONFIG - Peripheral System Configuration for HRCAL1

Figure 3-132 HRCAL1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-126 HRCAL1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.106 HRCAL2 Register (Offset = 61Ch) [Reset = 000000C0h]

HRCAL2 is shown in Figure 3-133 and described in Table 3-127.

Return to the Summary Table.

PER23SYSCONFIG - Peripheral System Configuration for HRCAL2

Figure 3-133 HRCAL2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-127 HRCAL2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.107 ECAP1 Register (Offset = 620h) [Reset = 000000C0h]

ECAP1 is shown in Figure 3-134 and described in Table 3-128.

Return to the Summary Table.

PER24SYSCONFIG - Peripheral System Configuration for ECAP1

Figure 3-134 ECAP1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-128 ECAP1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.108 ECAP2 Register (Offset = 624h) [Reset = 000000C0h]

ECAP2 is shown in Figure 3-135 and described in Table 3-129.

Return to the Summary Table.

PER25SYSCONFIG - Peripheral System Configuration for ECAP2

Figure 3-135 ECAP2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-129 ECAP2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.109 ECAP3 Register (Offset = 628h) [Reset = 000000C0h]

ECAP3 is shown in Figure 3-136 and described in Table 3-130.

Return to the Summary Table.

PER26SYSCONFIG - Peripheral System Configuration for ECAP3

Figure 3-136 ECAP3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-130 ECAP3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.110 ECAP4 Register (Offset = 62Ch) [Reset = 000000C0h]

ECAP4 is shown in Figure 3-137 and described in Table 3-131.

Return to the Summary Table.

PER27SYSCONFIG - Peripheral System Configuration for ECAP4

Figure 3-137 ECAP4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-131 ECAP4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.111 ECAP5 Register (Offset = 630h) [Reset = 000000C0h]

ECAP5 is shown in Figure 3-138 and described in Table 3-132.

Return to the Summary Table.

PER28SYSCONFIG - Peripheral System Configuration for ECAP5

Figure 3-138 ECAP5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-132 ECAP5 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.112 ECAP6 Register (Offset = 634h) [Reset = 000000C0h]

ECAP6 is shown in Figure 3-139 and described in Table 3-133.

Return to the Summary Table.

PER29SYSCONFIG - Peripheral System Configuration for ECAP6

Figure 3-139 ECAP6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-133 ECAP6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.113 EQEP1 Register (Offset = 638h) [Reset = 000000C0h]

EQEP1 is shown in Figure 3-140 and described in Table 3-134.

Return to the Summary Table.

PER30SYSCONFIG - Peripheral System Configuration for EQEP1

Figure 3-140 EQEP1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-134 EQEP1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.114 EQEP2 Register (Offset = 63Ch) [Reset = 000000C0h]

EQEP2 is shown in Figure 3-141 and described in Table 3-135.

Return to the Summary Table.

PER31SYSCONFIG - Peripheral System Configuration for EQEP2

Figure 3-141 EQEP2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-135 EQEP2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.115 EQEP3 Register (Offset = 640h) [Reset = 000000C0h]

EQEP3 is shown in Figure 3-142 and described in Table 3-136.

Return to the Summary Table.

PER32SYSCONFIG - Peripheral System Configuration for EQEP3

Figure 3-142 EQEP3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-136 EQEP3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.116 EQEP4 Register (Offset = 644h) [Reset = 000000C0h]

EQEP4 is shown in Figure 3-143 and described in Table 3-137.

Return to the Summary Table.

PER33SYSCONFIG - Peripheral System Configuration for EQEP4

Figure 3-143 EQEP4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-137 EQEP4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.117 EQEP5 Register (Offset = 648h) [Reset = 000000C0h]

EQEP5 is shown in Figure 3-144 and described in Table 3-138.

Return to the Summary Table.

PER34SYSCONFIG - Peripheral System Configuration for EQEP5

Figure 3-144 EQEP5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-138 EQEP5 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.118 EQEP6 Register (Offset = 64Ch) [Reset = 000000C0h]

EQEP6 is shown in Figure 3-145 and described in Table 3-139.

Return to the Summary Table.

PER35SYSCONFIG - Peripheral System Configuration for EQEP6

Figure 3-145 EQEP6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-139 EQEP6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.119 SDFM1 Register (Offset = 650h) [Reset = 000000C0h]

SDFM1 is shown in Figure 3-146 and described in Table 3-140.

Return to the Summary Table.

PER36SYSCONFIG - Peripheral System Configuration for SDFM1

Figure 3-146 SDFM1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-140 SDFM1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.120 SDFM2 Register (Offset = 654h) [Reset = 000000C0h]

SDFM2 is shown in Figure 3-147 and described in Table 3-141.

Return to the Summary Table.

PER37SYSCONFIG - Peripheral System Configuration for SDFM2

Figure 3-147 SDFM2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-141 SDFM2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.121 SDFM3 Register (Offset = 658h) [Reset = 000000C0h]

SDFM3 is shown in Figure 3-148 and described in Table 3-142.

Return to the Summary Table.

PER38SYSCONFIG - Peripheral System Configuration for SDFM3

Figure 3-148 SDFM3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-142 SDFM3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.122 SDFM4 Register (Offset = 65Ch) [Reset = 000000C0h]

SDFM4 is shown in Figure 3-149 and described in Table 3-143.

Return to the Summary Table.

PER39SYSCONFIG - Peripheral System Configuration for SDFM4

Figure 3-149 SDFM4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-143 SDFM4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.123 UARTA Register (Offset = 660h) [Reset = 000000C0h]

UARTA is shown in Figure 3-150 and described in Table 3-144.

Return to the Summary Table.

PER40SYSCONFIG - Peripheral System Configuration for UARTA

Figure 3-150 UARTA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-144 UARTA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.124 UARTB Register (Offset = 664h) [Reset = 000000C0h]

UARTB is shown in Figure 3-151 and described in Table 3-145.

Return to the Summary Table.

PER41SYSCONFIG - Peripheral System Configuration for UARTB

Figure 3-151 UARTB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-145 UARTB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.125 UARTC Register (Offset = 668h) [Reset = 000000C0h]

UARTC is shown in Figure 3-152 and described in Table 3-146.

Return to the Summary Table.

PER42SYSCONFIG - Peripheral System Configuration for UARTC

Figure 3-152 UARTC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-146 UARTC Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.126 UARTD Register (Offset = 66Ch) [Reset = 000000C0h]

UARTD is shown in Figure 3-153 and described in Table 3-147.

Return to the Summary Table.

PER43SYSCONFIG - Peripheral System Configuration for UARTD

Figure 3-153 UARTD Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-147 UARTD Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.127 UARTE Register (Offset = 670h) [Reset = 000000C0h]

UARTE is shown in Figure 3-154 and described in Table 3-148.

Return to the Summary Table.

PER44SYSCONFIG - Peripheral System Configuration for UARTE

Figure 3-154 UARTE Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-148 UARTE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.128 UARTF Register (Offset = 674h) [Reset = 000000C0h]

UARTF is shown in Figure 3-155 and described in Table 3-149.

Return to the Summary Table.

PER45SYSCONFIG - Peripheral System Configuration for UARTF

Figure 3-155 UARTF Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-149 UARTF Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.129 SPIA Register (Offset = 678h) [Reset = 000000C0h]

SPIA is shown in Figure 3-156 and described in Table 3-150.

Return to the Summary Table.

PER46SYSCONFIG - Peripheral System Configuration for SPIA

Figure 3-156 SPIA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-150 SPIA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.130 SPIB Register (Offset = 67Ch) [Reset = 000000C0h]

SPIB is shown in Figure 3-157 and described in Table 3-151.

Return to the Summary Table.

PER47SYSCONFIG - Peripheral System Configuration for SPIB

Figure 3-157 SPIB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-151 SPIB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.131 SPIC Register (Offset = 680h) [Reset = 000000C0h]

SPIC is shown in Figure 3-158 and described in Table 3-152.

Return to the Summary Table.

PER48SYSCONFIG - Peripheral System Configuration for SPIC

Figure 3-158 SPIC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-152 SPIC Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.132 SPID Register (Offset = 684h) [Reset = 000000C0h]

SPID is shown in Figure 3-159 and described in Table 3-153.

Return to the Summary Table.

PER49SYSCONFIG - Peripheral System Configuration for SPID

Figure 3-159 SPID Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-153 SPID Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.133 SPIE Register (Offset = 688h) [Reset = 000000C0h]

SPIE is shown in Figure 3-160 and described in Table 3-154.

Return to the Summary Table.

PER50SYSCONFIG - Peripheral System Configuration for SPIE

Figure 3-160 SPIE Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-154 SPIE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.134 I2CA Register (Offset = 68Ch) [Reset = 000000C0h]

I2CA is shown in Figure 3-161 and described in Table 3-155.

Return to the Summary Table.

PER51SYSCONFIG - Peripheral System Configuration for I2CA

Figure 3-161 I2CA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-155 I2CA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.135 I2CB Register (Offset = 690h) [Reset = 000000C0h]

I2CB is shown in Figure 3-162 and described in Table 3-156.

Return to the Summary Table.

PER52SYSCONFIG - Peripheral System Configuration for I2CB

Figure 3-162 I2CB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-156 I2CB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.136 PMBUSA Register (Offset = 694h) [Reset = 000000C0h]

PMBUSA is shown in Figure 3-163 and described in Table 3-157.

Return to the Summary Table.

PER53SYSCONFIG - Peripheral System Configuration for PMBUSA

Figure 3-163 PMBUSA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-157 PMBUSA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.137 LINA Register (Offset = 698h) [Reset = 000000C0h]

LINA is shown in Figure 3-164 and described in Table 3-158.

Return to the Summary Table.

PER54SYSCONFIG - Peripheral System Configuration for LINA

Figure 3-164 LINA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-158 LINA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.138 LINB Register (Offset = 69Ch) [Reset = 000000C0h]

LINB is shown in Figure 3-165 and described in Table 3-159.

Return to the Summary Table.

PER55SYSCONFIG - Peripheral System Configuration for LINB

Figure 3-165 LINB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-159 LINB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.139 MCANA Register (Offset = 6A0h) [Reset = 000000C0h]

MCANA is shown in Figure 3-166 and described in Table 3-160.

Return to the Summary Table.

PER56SYSCONFIG - Peripheral System Configuration for MCANA

Figure 3-166 MCANA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-160 MCANA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.140 MCANB Register (Offset = 6A4h) [Reset = 000000C0h]

MCANB is shown in Figure 3-167 and described in Table 3-161.

Return to the Summary Table.

PER57SYSCONFIG - Peripheral System Configuration for MCANB

Figure 3-167 MCANB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-161 MCANB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.141 MCANC Register (Offset = 6A8h) [Reset = 000000C0h]

MCANC is shown in Figure 3-168 and described in Table 3-162.

Return to the Summary Table.

PER58SYSCONFIG - Peripheral System Configuration for MCANC

Figure 3-168 MCANC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-162 MCANC Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.142 MCAND Register (Offset = 6ACh) [Reset = 000000C0h]

MCAND is shown in Figure 3-169 and described in Table 3-163.

Return to the Summary Table.

PER59SYSCONFIG - Peripheral System Configuration for MCAND

Figure 3-169 MCAND Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-163 MCAND Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.143 MCANE Register (Offset = 6B0h) [Reset = 000000C0h]

MCANE is shown in Figure 3-170 and described in Table 3-164.

Return to the Summary Table.

PER60SYSCONFIG - Peripheral System Configuration for MCANE

Figure 3-170 MCANE Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-164 MCANE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.144 MCANF Register (Offset = 6B4h) [Reset = 000000C0h]

MCANF is shown in Figure 3-171 and described in Table 3-165.

Return to the Summary Table.

PER61SYSCONFIG - Peripheral System Configuration for MCANF

Figure 3-171 MCANF Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-165 MCANF Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.145 ADCA Register (Offset = 6B8h) [Reset = 000000C0h]

ADCA is shown in Figure 3-172 and described in Table 3-166.

Return to the Summary Table.

PER62SYSCONFIG - Peripheral System Configuration for ADCA

Figure 3-172 ADCA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-166 ADCA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.146 ADCB Register (Offset = 6BCh) [Reset = 000000C0h]

ADCB is shown in Figure 3-173 and described in Table 3-167.

Return to the Summary Table.

PER63SYSCONFIG - Peripheral System Configuration for ADCB

Figure 3-173 ADCB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-167 ADCB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.147 ADCC Register (Offset = 6C0h) [Reset = 000000C0h]

ADCC is shown in Figure 3-174 and described in Table 3-168.

Return to the Summary Table.

PER64SYSCONFIG - Peripheral System Configuration for ADCC

Figure 3-174 ADCC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-168 ADCC Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.148 ADCD Register (Offset = 6C4h) [Reset = 000000C0h]

ADCD is shown in Figure 3-175 and described in Table 3-169.

Return to the Summary Table.

PER65SYSCONFIG - Peripheral System Configuration for ADCD

Figure 3-175 ADCD Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-169 ADCD Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.149 ADCE Register (Offset = 6C8h) [Reset = 000000C0h]

ADCE is shown in Figure 3-176 and described in Table 3-170.

Return to the Summary Table.

PER66SYSCONFIG - Peripheral System Configuration for ADCE

Figure 3-176 ADCE Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-170 ADCE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.150 CMPSS1 Register (Offset = 6CCh) [Reset = 000000C0h]

CMPSS1 is shown in Figure 3-177 and described in Table 3-171.

Return to the Summary Table.

PER67SYSCONFIG - Peripheral System Configuration for CMPSS1

Figure 3-177 CMPSS1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-171 CMPSS1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.151 CMPSS2 Register (Offset = 6D0h) [Reset = 000000C0h]

CMPSS2 is shown in Figure 3-178 and described in Table 3-172.

Return to the Summary Table.

PER68SYSCONFIG - Peripheral System Configuration for CMPSS2

Figure 3-178 CMPSS2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-172 CMPSS2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.152 CMPSS3 Register (Offset = 6D4h) [Reset = 000000C0h]

CMPSS3 is shown in Figure 3-179 and described in Table 3-173.

Return to the Summary Table.

PER69SYSCONFIG - Peripheral System Configuration for CMPSS3

Figure 3-179 CMPSS3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-173 CMPSS3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.153 CMPSS4 Register (Offset = 6D8h) [Reset = 000000C0h]

CMPSS4 is shown in Figure 3-180 and described in Table 3-174.

Return to the Summary Table.

PER70SYSCONFIG - Peripheral System Configuration for CMPSS4

Figure 3-180 CMPSS4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-174 CMPSS4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.154 CMPSS5 Register (Offset = 6DCh) [Reset = 000000C0h]

CMPSS5 is shown in Figure 3-181 and described in Table 3-175.

Return to the Summary Table.

PER71SYSCONFIG - Peripheral System Configuration for CMPSS5

Figure 3-181 CMPSS5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-175 CMPSS5 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.155 CMPSS6 Register (Offset = 6E0h) [Reset = 000000C0h]

CMPSS6 is shown in Figure 3-182 and described in Table 3-176.

Return to the Summary Table.

PER72SYSCONFIG - Peripheral System Configuration for CMPSS6

Figure 3-182 CMPSS6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-176 CMPSS6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.156 CMPSS7 Register (Offset = 6E4h) [Reset = 000000C0h]

CMPSS7 is shown in Figure 3-183 and described in Table 3-177.

Return to the Summary Table.

PER73SYSCONFIG - Peripheral System Configuration for CMPSS7

Figure 3-183 CMPSS7 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-177 CMPSS7 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.157 CMPSS8 Register (Offset = 6E8h) [Reset = 000000C0h]

CMPSS8 is shown in Figure 3-184 and described in Table 3-178.

Return to the Summary Table.

PER74SYSCONFIG - Peripheral System Configuration for CMPSS8

Figure 3-184 CMPSS8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-178 CMPSS8 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.158 CMPSS9 Register (Offset = 6ECh) [Reset = 000000C0h]

CMPSS9 is shown in Figure 3-185 and described in Table 3-179.

Return to the Summary Table.

PER75SYSCONFIG - Peripheral System Configuration for CMPSS9

Figure 3-185 CMPSS9 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-179 CMPSS9 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.159 CMPSS10 Register (Offset = 6F0h) [Reset = 000000C0h]

CMPSS10 is shown in Figure 3-186 and described in Table 3-180.

Return to the Summary Table.

PER76SYSCONFIG - Peripheral System Configuration for CMPSS10

Figure 3-186 CMPSS10 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-180 CMPSS10 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.160 CMPSS11 Register (Offset = 6F4h) [Reset = 000000C0h]

CMPSS11 is shown in Figure 3-187 and described in Table 3-181.

Return to the Summary Table.

PER77SYSCONFIG - Peripheral System Configuration for CMPSS11

Figure 3-187 CMPSS11 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-181 CMPSS11 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.161 CMPSS12 Register (Offset = 6F8h) [Reset = 000000C0h]

CMPSS12 is shown in Figure 3-188 and described in Table 3-182.

Return to the Summary Table.

PER78SYSCONFIG - Peripheral System Configuration for CMPSS12

Figure 3-188 CMPSS12 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-182 CMPSS12 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.162 DACA Register (Offset = 6FCh) [Reset = 000000C0h]

DACA is shown in Figure 3-189 and described in Table 3-183.

Return to the Summary Table.

PER79SYSCONFIG - Peripheral System Configuration for DACA

Figure 3-189 DACA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-183 DACA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.163 DACB Register (Offset = 700h) [Reset = 000000C0h]

DACB is shown in Figure 3-190 and described in Table 3-184.

Return to the Summary Table.

PER80SYSCONFIG - Peripheral System Configuration for DACB

Figure 3-190 DACB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-184 DACB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.164 CLB1 Register (Offset = 704h) [Reset = 000000C0h]

CLB1 is shown in Figure 3-191 and described in Table 3-185.

Return to the Summary Table.

PER81SYSCONFIG - Peripheral System Configuration for CLB1

Figure 3-191 CLB1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-185 CLB1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.165 CLB2 Register (Offset = 708h) [Reset = 000000C0h]

CLB2 is shown in Figure 3-192 and described in Table 3-186.

Return to the Summary Table.

PER82SYSCONFIG - Peripheral System Configuration for CLB2

Figure 3-192 CLB2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-186 CLB2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.166 CLB3 Register (Offset = 70Ch) [Reset = 000000C0h]

CLB3 is shown in Figure 3-193 and described in Table 3-187.

Return to the Summary Table.

PER83SYSCONFIG - Peripheral System Configuration for CLB3

Figure 3-193 CLB3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-187 CLB3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.167 CLB4 Register (Offset = 710h) [Reset = 000000C0h]

CLB4 is shown in Figure 3-194 and described in Table 3-188.

Return to the Summary Table.

PER84SYSCONFIG - Peripheral System Configuration for CLB4

Figure 3-194 CLB4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-188 CLB4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.168 CLB5 Register (Offset = 714h) [Reset = 000000C0h]

CLB5 is shown in Figure 3-195 and described in Table 3-189.

Return to the Summary Table.

PER85SYSCONFIG - Peripheral System Configuration for CLB5

Figure 3-195 CLB5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-189 CLB5 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.169 CLB6 Register (Offset = 718h) [Reset = 000000C0h]

CLB6 is shown in Figure 3-196 and described in Table 3-190.

Return to the Summary Table.

PER86SYSCONFIG - Peripheral System Configuration for CLB6

Figure 3-196 CLB6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-190 CLB6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.170 FSITXA Register (Offset = 71Ch) [Reset = 000000C0h]

FSITXA is shown in Figure 3-197 and described in Table 3-191.

Return to the Summary Table.

PER87SYSCONFIG - Peripheral System Configuration for FSITXA

Figure 3-197 FSITXA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-191 FSITXA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.171 FSITXB Register (Offset = 720h) [Reset = 000000C0h]

FSITXB is shown in Figure 3-198 and described in Table 3-192.

Return to the Summary Table.

PER88SYSCONFIG - Peripheral System Configuration for FSITXB

Figure 3-198 FSITXB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-192 FSITXB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.172 FSITXC Register (Offset = 724h) [Reset = 000000C0h]

FSITXC is shown in Figure 3-199 and described in Table 3-193.

Return to the Summary Table.

PER89SYSCONFIG - Peripheral System Configuration for FSITXC

Figure 3-199 FSITXC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-193 FSITXC Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.173 FSITXD Register (Offset = 728h) [Reset = 000000C0h]

FSITXD is shown in Figure 3-200 and described in Table 3-194.

Return to the Summary Table.

PER90SYSCONFIG - Peripheral System Configuration for FSITXD

Figure 3-200 FSITXD Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-194 FSITXD Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.174 FSIRXA Register (Offset = 72Ch) [Reset = 000000C0h]

FSIRXA is shown in Figure 3-201 and described in Table 3-195.

Return to the Summary Table.

PER91SYSCONFIG - Peripheral System Configuration for FSIRXA

Figure 3-201 FSIRXA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-195 FSIRXA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.175 FSIRXB Register (Offset = 730h) [Reset = 000000C0h]

FSIRXB is shown in Figure 3-202 and described in Table 3-196.

Return to the Summary Table.

PER92SYSCONFIG - Peripheral System Configuration for FSIRXB

Figure 3-202 FSIRXB Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-196 FSIRXB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.176 FSIRXC Register (Offset = 734h) [Reset = 000000C0h]

FSIRXC is shown in Figure 3-203 and described in Table 3-197.

Return to the Summary Table.

PER93SYSCONFIG - Peripheral System Configuration for FSIRXC

Figure 3-203 FSIRXC Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-197 FSIRXC Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.177 FSIRXD Register (Offset = 738h) [Reset = 000000C0h]

FSIRXD is shown in Figure 3-204 and described in Table 3-198.

Return to the Summary Table.

PER94SYSCONFIG - Peripheral System Configuration for FSIRXD

Figure 3-204 FSIRXD Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-198 FSIRXD Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.178 DCC1 Register (Offset = 73Ch) [Reset = 000000C0h]

DCC1 is shown in Figure 3-205 and described in Table 3-199.

Return to the Summary Table.

PER95SYSCONFIG - Peripheral System Configuration for DCC1

Figure 3-205 DCC1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-199 DCC1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.179 DCC2 Register (Offset = 740h) [Reset = 000000C0h]

DCC2 is shown in Figure 3-206 and described in Table 3-200.

Return to the Summary Table.

PER96SYSCONFIG - Peripheral System Configuration for DCC2

Figure 3-206 DCC2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-200 DCC2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.180 DCC3 Register (Offset = 744h) [Reset = 000000C0h]

DCC3 is shown in Figure 3-207 and described in Table 3-201.

Return to the Summary Table.

PER97SYSCONFIG - Peripheral System Configuration for DCC3

Figure 3-207 DCC3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-201 DCC3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.181 ETHERCATA Register (Offset = 748h) [Reset = 000000C0h]

ETHERCATA is shown in Figure 3-208 and described in Table 3-202.

Return to the Summary Table.

PER98SYSCONFIG - Peripheral System Configuration for ETHERCATA

Figure 3-208 ETHERCATA Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-202 ETHERCATA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.182 EPG1 Register (Offset = 74Ch) [Reset = 000000C0h]

EPG1 is shown in Figure 3-209 and described in Table 3-203.

Return to the Summary Table.

PER99SYSCONFIG - Peripheral System Configuration for EPG1

Figure 3-209 EPG1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-203 EPG1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.183 SENT1 Register (Offset = 750h) [Reset = 000000C0h]

SENT1 is shown in Figure 3-210 and described in Table 3-204.

Return to the Summary Table.

PER100SYSCONFIG - Peripheral System Configuration for SENT1

Figure 3-210 SENT1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-204 SENT1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.184 SENT2 Register (Offset = 754h) [Reset = 000000C0h]

SENT2 is shown in Figure 3-211 and described in Table 3-205.

Return to the Summary Table.

PER101SYSCONFIG - Peripheral System Configuration for SENT2

Figure 3-211 SENT2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-205 SENT2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.185 SENT3 Register (Offset = 758h) [Reset = 000000C0h]

SENT3 is shown in Figure 3-212 and described in Table 3-206.

Return to the Summary Table.

PER102SYSCONFIG - Peripheral System Configuration for SENT3

Figure 3-212 SENT3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-206 SENT3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.186 SENT4 Register (Offset = 75Ch) [Reset = 000000C0h]

SENT4 is shown in Figure 3-213 and described in Table 3-207.

Return to the Summary Table.

PER103SYSCONFIG - Peripheral System Configuration for SENT4

Figure 3-213 SENT4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-207 SENT4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.187 SENT5 Register (Offset = 760h) [Reset = 000000C0h]

SENT5 is shown in Figure 3-214 and described in Table 3-208.

Return to the Summary Table.

PER104SYSCONFIG - Peripheral System Configuration for SENT5

Figure 3-214 SENT5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-208 SENT5 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.188 SENT6 Register (Offset = 764h) [Reset = 000000C0h]

SENT6 is shown in Figure 3-215 and described in Table 3-209.

Return to the Summary Table.

PER105SYSCONFIG - Peripheral System Configuration for SENT6

Figure 3-215 SENT6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-209 SENT6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.189 ADCCHECKER1 Register (Offset = 768h) [Reset = 000000C0h]

ADCCHECKER1 is shown in Figure 3-216 and described in Table 3-210.

Return to the Summary Table.

PER106SYSCONFIG - Peripheral System Configuration for ADCCHECKER1

Figure 3-216 ADCCHECKER1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-210 ADCCHECKER1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.190 ADCCHECKER2 Register (Offset = 76Ch) [Reset = 000000C0h]

ADCCHECKER2 is shown in Figure 3-217 and described in Table 3-211.

Return to the Summary Table.

PER107SYSCONFIG - Peripheral System Configuration for ADCCHECKER2

Figure 3-217 ADCCHECKER2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-211 ADCCHECKER2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.191 ADCCHECKER3 Register (Offset = 770h) [Reset = 000000C0h]

ADCCHECKER3 is shown in Figure 3-218 and described in Table 3-212.

Return to the Summary Table.

PER108SYSCONFIG - Peripheral System Configuration for ADCCHECKER3

Figure 3-218 ADCCHECKER3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-212 ADCCHECKER3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.192 ADCCHECKER4 Register (Offset = 774h) [Reset = 000000C0h]

ADCCHECKER4 is shown in Figure 3-219 and described in Table 3-213.

Return to the Summary Table.

PER109SYSCONFIG - Peripheral System Configuration for ADCCHECKER4

Figure 3-219 ADCCHECKER4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-213 ADCCHECKER4 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.193 ADCCHECKER5 Register (Offset = 778h) [Reset = 000000C0h]

ADCCHECKER5 is shown in Figure 3-220 and described in Table 3-214.

Return to the Summary Table.

PER110SYSCONFIG - Peripheral System Configuration for ADCCHECKER5

Figure 3-220 ADCCHECKER5 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-214 ADCCHECKER5 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.194 ADCCHECKER6 Register (Offset = 77Ch) [Reset = 000000C0h]

ADCCHECKER6 is shown in Figure 3-221 and described in Table 3-215.

Return to the Summary Table.

PER111SYSCONFIG - Peripheral System Configuration for ADCCHECKER6

Figure 3-221 ADCCHECKER6 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-215 ADCCHECKER6 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.195 ADCCHECKER7 Register (Offset = 780h) [Reset = 000000C0h]

ADCCHECKER7 is shown in Figure 3-222 and described in Table 3-216.

Return to the Summary Table.

PER112SYSCONFIG - Peripheral System Configuration for ADCCHECKER7

Figure 3-222 ADCCHECKER7 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-216 ADCCHECKER7 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.196 ADCCHECKER8 Register (Offset = 784h) [Reset = 000000C0h]

ADCCHECKER8 is shown in Figure 3-223 and described in Table 3-217.

Return to the Summary Table.

PER113SYSCONFIG - Peripheral System Configuration for ADCCHECKER8

Figure 3-223 ADCCHECKER8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-217 ADCCHECKER8 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.197 ADCCHECKER9 Register (Offset = 788h) [Reset = 000000C0h]

ADCCHECKER9 is shown in Figure 3-224 and described in Table 3-218.

Return to the Summary Table.

PER114SYSCONFIG - Peripheral System Configuration for ADCCHECKER9

Figure 3-224 ADCCHECKER9 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-218 ADCCHECKER9 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.198 ADCCHECKER10 Register (Offset = 78Ch) [Reset = 000000C0h]

ADCCHECKER10 is shown in Figure 3-225 and described in Table 3-219.

Return to the Summary Table.

PER115SYSCONFIG - Peripheral System Configuration for ADCCHECKER10

Figure 3-225 ADCCHECKER10 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-219 ADCCHECKER10 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.199 ADCSEAGGRCPU1 Register (Offset = 790h) [Reset = 000000C0h]

ADCSEAGGRCPU1 is shown in Figure 3-226 and described in Table 3-220.

Return to the Summary Table.

PER116SYSCONFIG - Peripheral System Configuration for ADCSEAGGRCPU1

Figure 3-226 ADCSEAGGRCPU1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-220 ADCSEAGGRCPU1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.200 ADCSEAGGRCPU2 Register (Offset = 794h) [Reset = 000000C0h]

ADCSEAGGRCPU2 is shown in Figure 3-227 and described in Table 3-221.

Return to the Summary Table.

PER117SYSCONFIG - Peripheral System Configuration for ADCSEAGGRCPU2

Figure 3-227 ADCSEAGGRCPU2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-221 ADCSEAGGRCPU2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.201 ADCSEAGGRCPU3 Register (Offset = 798h) [Reset = 000000C0h]

ADCSEAGGRCPU3 is shown in Figure 3-228 and described in Table 3-222.

Return to the Summary Table.

PER118SYSCONFIG - Peripheral System Configuration for ADCSEAGGRCPU3

Figure 3-228 ADCSEAGGRCPU3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-222 ADCSEAGGRCPU3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.202 RTDMA1CH Register (Offset = 7A8h) [Reset = 000000C0h]

RTDMA1CH is shown in Figure 3-229 and described in Table 3-223.

Return to the Summary Table.

PER122SYSCONFIG - Peripheral System Configuration for RTDMA1CH

Figure 3-229 RTDMA1CH Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-223 RTDMA1CH Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.203 RTDMA2CH Register (Offset = 7ACh) [Reset = 000000C0h]

RTDMA2CH is shown in Figure 3-230 and described in Table 3-224.

Return to the Summary Table.

PER123SYSCONFIG - Peripheral System Configuration for RTDMA2CH

Figure 3-230 RTDMA2CH Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-224 RTDMA2CH Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.204 WADI1 Register (Offset = 7B0h) [Reset = 000000C0h]

WADI1 is shown in Figure 3-231 and described in Table 3-225.

Return to the Summary Table.

PER124SYSCONFIG - Peripheral System Configuration for WADI1

Figure 3-231 WADI1 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-225 WADI1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.205 WADI2 Register (Offset = 7B4h) [Reset = 000000C0h]

WADI2 is shown in Figure 3-232 and described in Table 3-226.

Return to the Summary Table.

PER125SYSCONFIG - Peripheral System Configuration for WADI2

Figure 3-232 WADI2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-226 WADI2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.206 INPUTXBARFlags Register (Offset = 7B8h) [Reset = 000000C0h]

INPUTXBARFlags is shown in Figure 3-233 and described in Table 3-227.

Return to the Summary Table.

PER126SYSCONFIG - Peripheral System Configuration for INPUTXBARFlags

Figure 3-233 INPUTXBARFlags Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-227 INPUTXBARFlags Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.207 OUTPUTXBARFlags Register (Offset = 7BCh) [Reset = 000000C0h]

OUTPUTXBARFlags is shown in Figure 3-234 and described in Table 3-228.

Return to the Summary Table.

PER127SYSCONFIG - Peripheral System Configuration for OUTPUTXBARFlags

Figure 3-234 OUTPUTXBARFlags Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-228 OUTPUTXBARFlags Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.208 DLTFIFORegs Register (Offset = 7C0h) [Reset = 000000C0h]

DLTFIFORegs is shown in Figure 3-235 and described in Table 3-229.

Return to the Summary Table.

PER128SYSCONFIG - Peripheral System Configuration for DLTFIFORegs

Figure 3-235 DLTFIFORegs Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-229 DLTFIFORegs Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.209 ADC_GLOBAL_REGS Register (Offset = 7C4h) [Reset = 000000C0h]

ADC_GLOBAL_REGS is shown in Figure 3-236 and described in Table 3-230.

Return to the Summary Table.

PER129SYSCONFIG - Peripheral System Configuration for ADC_GLOBAL_REGS

Figure 3-236 ADC_GLOBAL_REGS Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-230 ADC_GLOBAL_REGS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.210 Error_Aggregator Register (Offset = 7C8h) [Reset = 000000C0h]

Error_Aggregator is shown in Figure 3-237 and described in Table 3-231.

Return to the Summary Table.

PER130SYSCONFIG - Peripheral System Configuration for Error_Aggregator

Figure 3-237 Error_Aggregator Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-231 Error_Aggregator Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.211 ESM Register (Offset = 7CCh) [Reset = 000000C0h]

ESM is shown in Figure 3-238 and described in Table 3-232.

Return to the Summary Table.

PER131SYSCONFIG - Peripheral System Configuration for ESM ESMCPU1/2/3 and ESMSYS

Figure 3-238 ESM Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
DBGHALTENSTANDBYENCPUSELFRAMESEL
R/W-1hR/W-1hR/W-0hR/W-0h
Table 3-232 ESM Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7DBGHALTENR/W1h0 : Peripheral DBGHALT signal NOT activated when respective CPU (selected by CPUSEL) enters HALT mode
1 : Peripheral DBGHALT signal activated when respective CPU (selected by CPUSEL) enters HALT mode

Reset type: CPU1.SYSRSn

6STANDBYENR/W1h0 : Peripheral NOT clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode
1 : Peripheral clock gated when respective CPU (selected by CPUSEL) enters STANDBY mode

Reset type: CPU1.SYSRSn

5-3CPUSELR/W0hPeripheral CPU selection logic

000: Connected to CPU1 (default)
001: Connected to CPU2
010: Connected to CPU3
011: Reserved
1xx: Reserved

Reset type: CPU1.SYSRSn

2-0FRAMESELR/W0hPeripheral selection logic for FRAME

000: Connected to FRAME0 (default)
001: Connected to FRAME1
010: Connected to FRAME2
011: Connected to FRAME3
1xx: Reserved

Reset type: CPU1.SYSRSn

3.13.2.212 PARITY_TEST Register (Offset = 7E4h) [Reset = 00000000h]

PARITY_TEST is shown in Figure 3-239 and described in Table 3-233.

Return to the Summary Table.

Enables parity test

Figure 3-239 PARITY_TEST Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDTESTEN
R-0hR/W-0h
Table 3-233 PARITY_TEST Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0TESTENR/W0h1010: Parity test feature is enabled
All other values: Parity test feature is disabled

Note:
(1) When the parity test feature is enabled, actual registers are not accessible in the memory map. Instead, the parity values (final XOR output indicating the parity error) are accessible. Parity is computed for every byte and the corresponding parity error value is available at the bit-0 of every byte. Value of '1' written to the parity bit after enabling the parity test feature can be used to inject the error by inverting the stored parity value.
(2) It is recommended to leave the field as 0101 or 0000 after completing the parity test.

Reset type: SYSRSn