SWCU195A December   2024  – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

6.6.8 CKMD Registers

Table 6-105 lists the memory-mapped registers for the CKMD registers. All register offset addresses not listed in Table 6-105 should be considered as reserved locations and the register contents should not be modified.

Table 6-105 CKMD Registers
OffsetAcronymRegister NameSection
0hDESCIP DescriptionSection 6.6.8.1
44hIMASKInterrupt mask.Section 6.6.8.2
48hRISRaw interrupt flag registerSection 6.6.8.3
4ChMISMasked interrupt flag registerSection 6.6.8.4
50hISETInterrupt flag set registerSection 6.6.8.5
54hICLRInterrupt flag clear registerSection 6.6.8.6
58hIMSETInterrupt mask set registerSection 6.6.8.7
5ChIMCLRInterrupt mask clear register.Section 6.6.8.8
80hHFOSCCTLInternal. Only to be used through TI provided API.Section 6.6.8.9
84hHFXTCTLHigh frequency crystal controlSection 6.6.8.10
8ChLFOSCCTLLow frequency oscillator controlSection 6.6.8.11
90hLFXTCTLLow frequency crystal controlSection 6.6.8.12
94hLFQUALCTLLow frequency clock qualification controlSection 6.6.8.13
98hLFINCCTLLow frequency time increment controlSection 6.6.8.14
9ChLFINCOVRLow frequency time increment override controlSection 6.6.8.15
A0hAMPADCCTLInternal. Only to be used through TI provided API.Section 6.6.8.16
A4hHFTRACKCTLHigh frequency tracking loop controlSection 6.6.8.17
A8hLDOCTLInternal. Only to be used through TI provided API.Section 6.6.8.18
AChNABIASCTLNanoamp-bias controlSection 6.6.8.19
B0hLFMONCTLLow-frequency clock-monitor controlSection 6.6.8.20
B4hLFINCCTL2Low frequency time increment control-2Section 6.6.8.21
C0hLFCLKSELLow frequency clock selectionSection 6.6.8.22
C4hTDCCLKSELInternal. Only to be used through TI provided API.Section 6.6.8.23
C8hADCCLKSELADC clock selectionSection 6.6.8.24
E0hLFCLKSTATLow-frequency clock statusSection 6.6.8.25
E4hHFXTSTATHFXT status informationSection 6.6.8.26
E8hAMPADCSTATInternal. Only to be used through TI provided API.Section 6.6.8.27
EChTRACKSTATHF tracking loop status informationSection 6.6.8.28
F0hAMPSTATHFXT Amplitude Compensation StatusSection 6.6.8.29
F4hLFCLKSTAT2Low-frequency clock status-2Section 6.6.8.30
100hATBCTL0Internal. Only to be used through TI provided API.Section 6.6.8.31
104hATBCTL1Internal. Only to be used through TI provided API.Section 6.6.8.32
108hDTBCTLDigital test bus mux controlSection 6.6.8.33
10ChDTBCTL2Digital test bus mux controlSection 6.6.8.34
110hTRIM0Internal. Only to be used through TI provided API.Section 6.6.8.35
114hTRIM1Internal. Only to be used through TI provided API.Section 6.6.8.36
118hHFXTINITInitial values for HFXT rampingSection 6.6.8.37
11ChHFXTTARGTarget values for HFXT rampingSection 6.6.8.38
120hHFXTDYNAlternative target values for HFXT configurationSection 6.6.8.39
124hAMPCFG0Amplitude Compensation Configuration 0Section 6.6.8.40
128hAMPCFG1Amplitude Compensation Configuration 1Section 6.6.8.41
12ChLOOPCFGConfiguration Register for the Tracking LoopSection 6.6.8.42
130hLOOPCFG1Configuration Register for underclocking HFOSCSection 6.6.8.43
140hAFOSCCTLAudio frequency oscillator controlSection 6.6.8.44
144hAFTRACKCTLAudio frequency tracking loop controlSection 6.6.8.45
148hBANDGAPCTLInternal. Only to be used through TI provided API.Section 6.6.8.46
150hAFCLKSELAudio clock selectionSection 6.6.8.47
154hCANCLKSELCAN clock selectionSection 6.6.8.48
160hTRACKSTATAFAF tracking loop status informationSection 6.6.8.49
164hTRACKSTATAF1AF tracking loop status informationSection 6.6.8.50
168hTRACKSTATAF2AF tracking loop status informationSection 6.6.8.51
170hLOOPCFGAFConfiguration Register for the Audio frequency Tracking LoopSection 6.6.8.52
200hCTLControlSection 6.6.8.53
204hSTATStatusSection 6.6.8.54
208hRESULTResultSection 6.6.8.55
20ChSATCFGSaturation ConfigurationSection 6.6.8.56
210hTRIGSRCTrigger SourceSection 6.6.8.57
214hTRIGCNTTrigger CounterSection 6.6.8.58
218hTRIGCNTLOADTrigger Counter LoadSection 6.6.8.59
21ChTRIGCNTCFGTrigger Counter ConfigurationSection 6.6.8.60
220hPRECTLPrescaler ControlSection 6.6.8.61
224hPRECNTRPrescaler CounterSection 6.6.8.62
300hCNTWDT counter value registerSection 6.6.8.63
304hTESTWDT test mode registerSection 6.6.8.64
308hLOCKWDT lock registerSection 6.6.8.65

Complex bit access types are encoded to fit into small table cells. Table 6-106 shows the codes that are used for access types in this section.

Table 6-106 CKMD Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.8.1 DESC Register (Offset = 0h) [Reset = 00000000h]

DESC is shown in Table 6-107.

Return to the Summary Table.

IP Description

Table 6-107 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR9B4BhModule identifier
15-12STDIPOFFR1hStandard IP MMR block offset
11-8RESERVEDR0hReserved
7-4MAJREVR0hMajor revision
3-0MINREVR0hMinor revision

6.6.8.2 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 6-108.

Return to the Summary Table.

Interrupt mask.
This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 6-108 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23HFOSCSETTLEDR/W0hIndicates that HFOSC has settled, based on LOOPCFG.SETTLED_TARGET and LOOPCFG1.SETTLEIRQ
22LFGEARRSTRTLIMR/W0hIndicates that the LFINC filter gearing mechanism has restarted more than LFINCCTL2.GEARRSTRTLIM
21RESERVEDR0hReserved
20SYSUNDERCLOCKEDR/W0hIndicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running.
19AFOSCGOODR/W0hAFOSC good indication.
18TRACKREFAFOORR/W0hOut-of-range indication from the AFOSC tracking loop.
Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.
17LFTICKR/W0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTR/W0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDR/W0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGR/W0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGER/W0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSR/W0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORR/W0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODR/W0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDR/W0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONER/W0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDR/W0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDR/W0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDR/W0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORR/W0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSR/W0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODR/W0hHFXT amplitude good indication.
1HFXTFAULTR/W0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODR/W0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.6.8.3 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 6-109.

Return to the Summary Table.

Raw interrupt flag register

Table 6-109 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23HFOSCSETTLEDR0hIndicates that HFOSC has settled, based on LOOPCFG.SETTLED_TARGET and LOOPCFG1.SETTLEIRQ
22LFGEARRSTRTLIMR0hIndicates that the LFINC filter gearing mechanism has restarted more than LFINCCTL2.GEARRSTRTLIM
21RESERVEDR0hReserved
20SYSUNDERCLOCKEDR0hIndicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running.
19AFOSCGOODR0hAFOSC good indication.
18TRACKREFAFOORR0hOut-of-range indication from the AFOSC tracking loop.
Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.
17LFTICKR0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTR0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDR0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGR0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGER0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSR0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORR0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODR0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDR0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONER0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDR0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDR0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDR0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORR0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSR0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODR0hHFXT amplitude good indication.
1HFXTFAULTR0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODR0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.6.8.4 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 6-110.

Return to the Summary Table.

Masked interrupt flag register

Table 6-110 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23HFOSCSETTLEDR0hIndicates that HFOSC has settled, based on LOOPCFG.SETTLED_TARGET and LOOPCFG1.SETTLEIRQ
22LFGEARRSTRTLIMR0hIndicates that the LFINC filter gearing mechanism has restarted more than LFINCCTL2.GEARRSTRTLIM
21RESERVEDR0hReserved
20SYSUNDERCLOCKEDR0hIndicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running.
19AFOSCGOODR0hAFOSC good indication.
18TRACKREFAFOORR0hOut-of-range indication from the AFOSC tracking loop.
Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.
17LFTICKR0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTR0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDR0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGR0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGER0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSR0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORR0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODR0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDR0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONER0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDR0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDR0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDR0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORR0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSR0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODR0hHFXT amplitude good indication.
1HFXTFAULTR0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODR0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.6.8.5 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 6-111.

Return to the Summary Table.

Interrupt flag set register

Table 6-111 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23HFOSCSETTLEDW0hIndicates that HFOSC has settled, based on LOOPCFG.SETTLED_TARGET and LOOPCFG1.SETTLEIRQ
22LFGEARRSTRTLIMW0hIndicates that the LFINC filter gearing mechanism has restarted more than LFINCCTL2.GEARRSTRTLIM
21RESERVEDR0hReserved
20SYSUNDERCLOCKEDW0hIndicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running.
19AFOSCGOODW0hAFOSC good indication.
18TRACKREFAFOORW0hOut-of-range indication from the AFOSC tracking loop.
Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.
17LFTICKW0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTW0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDW0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGW0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGEW0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSW0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORW0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODW0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDW0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONEW0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDW0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDW0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDW0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORW0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSW0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODW0hHFXT amplitude good indication.
1HFXTFAULTW0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODW0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.6.8.6 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 6-112.

Return to the Summary Table.

Interrupt flag clear register

Table 6-112 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23HFOSCSETTLEDW0hIndicates that HFOSC has settled, based on LOOPCFG.SETTLED_TARGET and LOOPCFG1.SETTLEIRQ
22LFGEARRSTRTLIMW0hIndicates that the LFINC filter gearing mechanism has restarted more than LFINCCTL2.GEARRSTRTLIM
21RESERVEDR0hReserved
20SYSUNDERCLOCKEDW0hIndicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running.
19AFOSCGOODW0hAFOSC good indication.
18TRACKREFAFOORW0hOut-of-range indication from the AFOSC tracking loop.
Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.
17LFTICKW0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTW0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDW0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGW0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGEW0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSW0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORW0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODW0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDW0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONEW0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDW0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDW0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDW0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORW0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSW0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODW0hHFXT amplitude good indication.
1HFXTFAULTW0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODW0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.6.8.7 IMSET Register (Offset = 58h) [Reset = 00000000h]

IMSET is shown in Table 6-113.

Return to the Summary Table.

Interrupt mask set register

Table 6-113 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23HFOSCSETTLEDW0hIndicates that HFOSC has settled, based on LOOPCFG.SETTLED_TARGET and LOOPCFG1.SETTLEIRQ
22LFGEARRSTRTLIMW0hIndicates that the LFINC filter gearing mechanism has restarted more than LFINCCTL2.GEARRSTRTLIM
21RESERVEDR0hReserved
20SYSUNDERCLOCKEDW0hIndicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running.
19AFOSCGOODW0hAFOSC good indication.
18TRACKREFAFOORW0hOut-of-range indication from the AFOSC tracking loop.
Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.
17LFTICKW0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTW0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDW0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGW0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGEW0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSW0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORW0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODW0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDW0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONEW0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDW0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDW0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDW0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORW0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSW0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODW0hHFXT amplitude good indication.
1HFXTFAULTW0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODW0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.6.8.8 IMCLR Register (Offset = 5Ch) [Reset = 00000000h]

IMCLR is shown in Table 6-114.

Return to the Summary Table.

Interrupt mask clear register.
Writing a 1 to a bit in this register will clear the corresponding IMASK bit.

Table 6-114 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23HFOSCSETTLEDW0hIndicates that HFOSC has settled, based on LOOPCFG.SETTLED_TARGET and LOOPCFG1.SETTLEIRQ
22LFGEARRSTRTLIMW0hIndicates that the LFINC filter gearing mechanism has restarted more than LFINCCTL2.GEARRSTRTLIM
21RESERVEDR0hReserved
20SYSUNDERCLOCKEDW0hIndicates system frequency has been lowered. It will be set only if HFTRACKCTL.UNDERCLK is appropriately configured and HFOSC tracking loop is not running.
19AFOSCGOODW0hAFOSC good indication.
18TRACKREFAFOORW0hOut-of-range indication from the AFOSC tracking loop.
Indicates that the reference clock frequency of AFOSC tracking loop is out-of-range.
17LFTICKW0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTW0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDW0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGW0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGEW0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock CLKSEL.PRELFCLK'
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSW0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORW0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODW0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDW0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONEW0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDW0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDW0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDW0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORW0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSW0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODW0hHFXT amplitude good indication.
1HFXTFAULTW0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODW0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.6.8.9 HFOSCCTL Register (Offset = 80h) [Reset = 00000000h]

HFOSCCTL is shown in Table 6-115.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-115 HFOSCCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24PWW0hInternal. Only to be used through TI provided API.
23-2RESERVEDR0hReserved
1FORCEOFFR/W0hInternal. Only to be used through TI provided API.
0QUALBYPR/W0hInternal. Only to be used through TI provided API.

6.6.8.10 HFXTCTL Register (Offset = 84h) [Reset = 00000000h]

HFXTCTL is shown in Table 6-116.

Return to the Summary Table.

High frequency crystal control

Table 6-116 HFXTCTL Register Field Descriptions
BitFieldTypeResetDescription
31AMPOVRR/W0hInternal. Only to be used through TI provided API.
30-27RESERVEDR0hReserved
26BIASENR/W0hInternal. Only to be used through TI provided API.
25LPBUFENR/W0hInternal. Only to be used through TI provided API.
24INJECTR/W0hInternal. Only to be used through TI provided API.
23QUALBYPR/W0hInternal. Only to be used through TI provided API.
22-20RESERVEDR0hReserved
19-8QUALDLYR/W0hSkip potentially unstable clock cycles after enabling HFXT.
Number of cycles skipped is 8*QUALDLY.
7TCXOMODER/W0hTemperature compensated crystal oscillator mode.
Set this bit if a TXCO is connected.
6TCXOTYPER/W0hType of temperature compensated crystal used.
Only has effect if TCXOMODE is set.
  • 0h = Use with clipped-sine TCXO
  • 1h = Use with CMOS TCXO
5-3RESERVEDR0hReserved
2AUTOENR/W0hInternal. Only to be used through TI provided API.
1HPBUFENR/W0hHigh performance clock buffer enable.
This bit controls the clock output for the RF PLL.
It is required for radio operation.
0ENR/W0hInternal. Only to be used through TI provided API.

6.6.8.11 LFOSCCTL Register (Offset = 8Ch) [Reset = 00000000h]

LFOSCCTL is shown in Table 6-117.

Return to the Summary Table.

Low frequency oscillator control

Table 6-117 LFOSCCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hLFOSC enable

6.6.8.12 LFXTCTL Register (Offset = 90h) [Reset = 00000000h]

LFXTCTL is shown in Table 6-118.

Return to the Summary Table.

Low frequency crystal control

Table 6-118 LFXTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14-13LEAKCOMPR/W0hLeakage compensation control
  • 0h = Full leakage compensation
  • 1h = Half leakage compensation
  • 3h = No leakage compensation
12BUFBIASR/W0hControl the BIAS current of the input amp in LP buffer
  • 0h = Minimum bias current: 25nA
  • 1h = Maximum bias current: 50nA
11-8AMPBIASR/W0hAdjust current mirror ratio into oscillator core. This value is depending on crystal and is set by FW. This field uses a 2's complement encoding.
7-6BIASBOOSTR/W0hBoost oscillator amplitude
This value depends on the crystal and needs to be configured by Firmware.
5-4REGBIASR/W0hRegulation loop bias resistor value
This value depends on the crystal and needs to be configured by Firmware.
3RESERVEDR0hReserved
2HPBUFENR/W0hControl the buffer used. In normal operation, low-power buffer is used in all device modes. The high-performance buffer is only used for test purposes.
1AMPREGMODER/W0hAmplitude regulation mode
  • 0h = Amplitude control loop enabled
  • 1h = Amplitude control loop disabled
0ENR/W0hLFXT enable

6.6.8.13 LFQUALCTL Register (Offset = 94h) [Reset = 00000000h]

LFQUALCTL is shown in Table 6-119.

Return to the Summary Table.

Low frequency clock qualification control

Table 6-119 LFQUALCTL Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-8MAXERRR/W20hMaximum LFCLK period error.
Value given in microseconds, 3 integer bits + 3 fractional bits.
7-0CONSECR/W64hNumber of consecutive times the LFCLK period error has to be
smaller than MAXERR to be considered "good".
Setting this value to 0 will bypass clock qualification,
and the "good" indicator will always be 1.

6.6.8.14 LFINCCTL Register (Offset = 98h) [Reset = 00000000h]

LFINCCTL is shown in Table 6-120.

Return to the Summary Table.

Low frequency time increment control

Table 6-120 LFINCCTL Register Field Descriptions
BitFieldTypeResetDescription
31PREVENTSTBYR/W1hControls if the LFINC filter prevents STANBY entry until settled.
  • 0h = Disable. Do not prevent STANDBY entry.
  • 1h = Enable. Prevent STANDBY entry.
30KEEPHFXTENR/W0hKeeps the HFXT enabled till the LFINC filter settles
  • 0h = Disable. Do not keep HFXT enabled.
  • 1h = Enable. Keep HFXT enabled.
29-8INTR/W001E8480hIntegral part of the LFINC filter.
This value is updated by Hardware to reflect the current state of the filter.
It can also be written to change the current state.
7STOPGEARR/W0hControls the final gear of the LFINC filter.
  • 0h = The LF filter is considered settled when LFCLKSTAT2.MAINGEAR reads 9 and LFCLKSTAT2.SUBGEAR reads 7. That means the LF filter will take 79 LF periods to settle provided the gear does not restarts.
  • 1h = The LF filter is considered settled when LFCLKSTAT2.MAINGEAR reads 8 and LFCLKSTAT2.SUBGEAR reads 7. That means the LF filter will take 71 LF periods to settle provided the gear does not restarts.
6-5ERRTHRR/W0hControls the threshold for gearing restart of the LFINC filter.
Only effective if GEARRSTRT is not ONETHR or TWOTHR.
  • 0h = Restart gearing on large error. Fewer false restarts, slower response on small frequency shifts.
  • 1h = Middle value towards LARGE.
  • 2h = Middle value towards SMALL.
  • 3h = Restart gearing on small error. Potentially more false restarts, faster response on small frequency shifts.
4-3GEARRSTRTR/W2hControls gearing restart of the LFINC filter.
  • 0h = Never restart gearing. Very stable filter value, but very slow response on frequency changes.
  • 1h = Restart gearing when the error accumulator crosses the threshold once.
  • 2h = Restart gearing when the error accumulator crosses the threshold twice in a row.
2SOFTRSTRTR/W1hUse a higher gear after re-enabling / wakeup.
The filter will require 16-24 LFCLK periods to settle (depending on STOPGEAR), but may respond faster to frequency changes during STANDBY.
  • 0h = Don't use soft gearing restarts
  • 1h = Use soft gearing restarts
1-0ENR/W1hEnable LFINC filter. Programming with a value of 0x3 will disable the LFINC filter
  • 0h = DISABLED
  • 1h = ENABLED
  • 2h = Enable based on HFOS getting settled. HFOSC gets settled after the tracking loop has updated equal to or more than LOOPCFG.SETTLED_TARGET times.

6.6.8.15 LFINCOVR Register (Offset = 9Ch) [Reset = 00000000h]

LFINCOVR is shown in Table 6-121.

Return to the Summary Table.

Low frequency time increment override control

Table 6-121 LFINCOVR Register Field Descriptions
BitFieldTypeResetDescription
31OVERRIDER/W0hOverride LF increment
Use the value provided in LFINC instead of the value calculated by Hardware.
30-22RESERVEDR0hReserved
21-0LFINCR/WXhLF increment value
This value is used when OVERRIDE is set to 1.
Otherwise the value is calculated automatically.
The current LFINC value can be read from [CKM.LFCLKSTAT.LFINC].

6.6.8.16 AMPADCCTL Register (Offset = A0h) [Reset = 00000000h]

AMPADCCTL is shown in Table 6-122.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-122 AMPADCCTL Register Field Descriptions
BitFieldTypeResetDescription
31SWOVRR/W0hInternal. Only to be used through TI provided API.
30-18RESERVEDR0hReserved
17PEAKDETENR/W0hInternal. Only to be used through TI provided API.
16ADCENR/W0hInternal. Only to be used through TI provided API.
15RESERVEDR0hReserved
14-8COMPVALR/W0hInternal. Only to be used through TI provided API.
7-5RESERVEDR0hReserved
4SRCSELR/W0hInternal. Only to be used through TI provided API.
3-2RESERVEDR0hReserved
1COMPSTRTR/W0hInternal. Only to be used through TI provided API.
0SARSTRTR/W0hInternal. Only to be used through TI provided API.

6.6.8.17 HFTRACKCTL Register (Offset = A4h) [Reset = 00000000h]

HFTRACKCTL is shown in Table 6-123.

Return to the Summary Table.

High frequency tracking loop control

Table 6-123 HFTRACKCTL Register Field Descriptions
BitFieldTypeResetDescription
31ENR/W0hEnable tracking loop.
30DSMBYPR/W0hBypass Delta-Sigma-Modulation of fine trim.
29-28UNDERCLKR/W0hWhen the HFOSC tracking loop is not running, this bitfield can be used to set the condition to automatically lower the HFOSC frequency. This will prevent frequency drift that may lead to SOC instability.
  • 0h = Disable
  • 1h = Timer event
  • 2h = Temperature event from Batmon
  • 3h = Temperature event from Batmon or Timer event
27-26REFCLKR/W0hSelect the reference clock for the tracking loop.
Change only while the tracking loop is disabled.
  • 0h = Select HFXT as reference clock.
  • 1h = Select LRF reference clock.
  • 2h = Select GPI as reference clock.
25-0RATIOR/W00400000hReference clock ratio. Ratio format is 2b.24b
RATIO = 24MHz / (2*reference-frequency) * 224
Commonly used reference clock frequencies are provided as enumerations.
  • 00400000h = Use for 48MHz reference clock
  • 01800000h = Use for 8MHz Reference clock
  • 03000000h = Use for 4MHz reference clock

6.6.8.18 LDOCTL Register (Offset = A8h) [Reset = 00000000h]

LDOCTL is shown in Table 6-124.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-124 LDOCTL Register Field Descriptions
BitFieldTypeResetDescription
31SWOVRR/W0hInternal. Only to be used through TI provided API.
30-5RESERVEDR0hReserved
4HFXTLVLENR/W0hInternal. Only to be used through TI provided API.
3STARTCTLR/W0hInternal. Only to be used through TI provided API.
2STARTR/W0hInternal. Only to be used through TI provided API.
1BYPASSR/W0hInternal. Only to be used through TI provided API.
0ENR/W0hInternal. Only to be used through TI provided API.

6.6.8.19 NABIASCTL Register (Offset = ACh) [Reset = 00000000h]

NABIASCTL is shown in Table 6-125.

Return to the Summary Table.

Nanoamp-bias control

Table 6-125 NABIASCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hEnable nanoamp-bias

6.6.8.20 LFMONCTL Register (Offset = B0h) [Reset = 00000000h]

LFMONCTL is shown in Table 6-126.

Return to the Summary Table.

Low-frequency clock-monitor control

Table 6-126 LFMONCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hEnable LFMONITOR.
Enable only after a LF clock source has been selected, enabled and is stable.
If LFMONITOR detects a clock loss, the system will be reset.

6.6.8.21 LFINCCTL2 Register (Offset = B4h) [Reset = 00000000h]

LFINCCTL2 is shown in Table 6-127.

Return to the Summary Table.

Low frequency time increment control-2

Table 6-127 LFINCCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31ADJUSTLFINCR/W0hAdjusts LFINC while transitioning from fake to real LF clock if necessary. For the adjustment to happen, tracking loop must be running.
30-10RESERVEDR0hReserved
9-4GEARRSTRTLIMR/W0hSpecifies the number of times gear could be restarted before raising an interrupt. It has no impact on the number of times gear can be reduced.
A value of 0 indicates that the interrupt mechanism is disabled
3-0GEARREDCNTR/W2hSpecifies the number by which gear should be reduced post standby exit

6.6.8.22 LFCLKSEL Register (Offset = C0h) [Reset = 00000000h]

LFCLKSEL is shown in Table 6-128.

Return to the Summary Table.

Low frequency clock selection

Table 6-128 LFCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2PRER/W0hSelect low frequency clock source for the PRELFCLK interrupt.
Can be used by Software to confirm that the clock is running and it's frequency is good, before selecting it in MAIN.
  • 0h = No clock. Output will be tied low.
  • 1h = Low frequency on-chip oscillator
  • 2h = Low frequency crystal oscillator
  • 3h = External LF clock through GPI.
1-0MAINR/W0hSelect the main low frequency clock source.
If running, this clock will be used to generate LFTICK and as CLKULL during STANDBY.
If not running, LFTICK will be generated from HFOSC and STANDBY entry will be prevented.
  • 0h = No LF clock selected. LFTICK will be generated from HFOSC, STANDBY entry will be prevented.
  • 1h = Low frequency on-chip oscillator
  • 2h = Low frequency crystal oscillator
  • 3h = External LF clock through GPI.

6.6.8.23 TDCCLKSEL Register (Offset = C4h) [Reset = 00000000h]

TDCCLKSEL is shown in Table 6-129.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-129 TDCCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0REFCLKR/W0hInternal. Only to be used through TI provided API.

6.6.8.24 ADCCLKSEL Register (Offset = C8h) [Reset = 00000000h]

ADCCLKSEL is shown in Table 6-130.

Return to the Summary Table.

ADC clock selection

Table 6-130 ADCCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SRCR/W0hSelect ADC clock source
Change only while ADC is disabled!
  • 0h = 48MHz CLKSVT
  • 1h = 48MHz HFXT

6.6.8.25 LFCLKSTAT Register (Offset = E0h) [Reset = 00000000h]

LFCLKSTAT is shown in Table 6-131.

Return to the Summary Table.

Low-frequency clock status

Table 6-131 LFCLKSTAT Register Field Descriptions
BitFieldTypeResetDescription
31GOODR0hLow frequency clock good
Note: This is only a coarse frequency check based on LFQUALCTL. The clock may not be accurate enough for timing purposes.
30-26RESERVEDR0hReserved
25FLTSETTLEDR0hLFINC filter is running and settled.
24LFTICKSRCR1hSource of LFTICK.
  • 0h = LFTICK generated from the selected LFCLK
  • 1h = LFTICK generated from CLKULL (LFCLK not available)
23-22LFINCSRCR3hSource of LFINC used by the RTC.
This value depends on LFINCOVR.OVERRIDE, LF clock availability, HF tracking loop status and the device state (ACTIVE/STANDBY).
  • 0h = Using measured value.;This value is updated by hardware and can be read from LFINC.
  • 1h = Using filtered / average value.;This value is updated by hardware and can be read and updated in LFINCCTL.INT.
  • 2h = Using override value from LFINCOVR.LFINC
  • 3h = Using FAKE LFTICKs with corresponding LFINC value.
21-0LFINCR001E8480hMeasured value of LFINC.
Given in microseconds with 16 fractional bits.
This value is calculated by Hardware.
It is the LFCLK period according to CLKULL cycles.

6.6.8.26 HFXTSTAT Register (Offset = E4h) [Reset = 00000000h]

HFXTSTAT is shown in Table 6-132.

Return to the Summary Table.

HFXT status information

Table 6-132 HFXTSTAT Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30-16STARTUPTIMER0hHFXT startup time
Can be used by software to plan starting HFXT ahead in time.
Measured whenever HFXT is enabled in CLKULL periods (24MHz), from HFXTCTL.EN until the clock is good for radio operation (amplitude compensation is settled).
15-2RESERVEDR0hReserved
1FAULTR0hHFXT clock fault
Indicates a lower than expected HFXT frequency.
HFXT will not recover from this fault, disabling and re-enabling HFXT is required.
0GOODR0hHFXT clock available.
The frequency is not necessarily good enough for radio operation.

6.6.8.27 AMPADCSTAT Register (Offset = E8h) [Reset = 00000000h]

AMPADCSTAT is shown in Table 6-133.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-133 AMPADCSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24COMPOUTR0hInternal. Only to be used through TI provided API.
23RESERVEDR0hReserved
22-16PEAKRAWR0hInternal. Only to be used through TI provided API.
15-8PEAKR0hInternal. Only to be used through TI provided API.
7RESERVEDR0hReserved
6-0BIASR0hInternal. Only to be used through TI provided API.

6.6.8.28 TRACKSTAT Register (Offset = ECh) [Reset = 00000000h]

TRACKSTAT is shown in Table 6-134.

Return to the Summary Table.

HF tracking loop status information

Table 6-134 TRACKSTAT Register Field Descriptions
BitFieldTypeResetDescription
31LOOPERRVLDR0hCurrent HFOSC tracking error valid
This bit is one if the tracking loop is running and the error value is valid.
30RESERVEDR0hReserved
29-16LOOPERRR0hCurrent HFOSC tracking error
This field uses the internal fractional representation (sign, 9 integer bits, 4 fractional bits).
15-13RESERVEDR0hReserved
12-0FINETRIMR1D80hCurrent HFOSC Fine-trim value
This field uses the internal fractional representation (sign, 5 integer bits, 7 fractional bits).
The actual trim value applied to the oscillator is delta-sigma modulated 6 bits non-signed
(inverted sign bit + integer bits).

6.6.8.29 AMPSTAT Register (Offset = F0h) [Reset = 00000000h]

AMPSTAT is shown in Table 6-135.

Return to the Summary Table.

HFXT Amplitude Compensation Status

Table 6-135 AMPSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-25STATER0hCurrent AMPCOMP FSM state.
  • 0h = FSM in idle state
  • 1h = Starting LDO
  • 2h = Second shutdown state
  • 3h = Injecting HFOSC for fast startup
  • 4h = Transition to HFXTTARG values
  • 5h = Initial amplitude ramping with HFXTINIT values
  • 6h = Amplitude down correction
  • 7h = Post injection settle wait
  • Ah = First shutdown state
  • Ch = TCXO settled state
  • Eh = Amplitude up correction
  • Fh = Settled state
24-18IDACR0hCurrent IDAC control value.
17-14IREFR0hCurrent IREF control value.
13-8Q2CAPR0hCurrent Q2CAP control value.
7-2Q1CAPR0hCurrent Q1CAP control value.
1CTRLATTARGETR0hHFXT control values match target values.
This applies to IREF, Q1CAP, Q2CAP values.
0AMPGOODR0hHFXT amplitude good

6.6.8.30 LFCLKSTAT2 Register (Offset = F4h) [Reset = 00000000h]

LFCLKSTAT2 is shown in Table 6-136.

Return to the Summary Table.

Low-frequency clock status-2

Table 6-136 LFCLKSTAT2 Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-4SUBGEARR0hThe value of sub gear in LF filter. It counts from 0 to 7.
3-0MAINGEARR0hThe value of main gear in LF filter. The main gear increments when the sub gear crosses 7.

6.6.8.31 ATBCTL0 Register (Offset = 100h) [Reset = 00000000h]

ATBCTL0 is shown in Table 6-137.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-137 ATBCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-0SELR/WXhInternal. Only to be used through TI provided API.

6.6.8.32 ATBCTL1 Register (Offset = 104h) [Reset = 00000000h]

ATBCTL1 is shown in Table 6-138.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-138 ATBCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18BGAPR/W0hInternal. Only to be used through TI provided API.
17-15AFOSCR/W0hInternal. Only to be used through TI provided API.
14-13LFOSCR/W0hInternal. Only to be used through TI provided API.
12NABIASR/W0hInternal. Only to be used through TI provided API.
11RESERVEDR0hReserved
10LFXTR/W0hInternal. Only to be used through TI provided API.
9-8LFMONR/W0hInternal. Only to be used through TI provided API.
7HFXTR/W0hInternal. Only to be used through TI provided API.
6-3RESERVEDR0hReserved
2-0HFOSCR/W0hInternal. Only to be used through TI provided API.

6.6.8.33 DTBCTL Register (Offset = 108h) [Reset = 00000000h]

DTBCTL is shown in Table 6-139.

Return to the Summary Table.

Digital test bus mux control

Table 6-139 DTBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-18DSEL2R/W0hInternal. Only to be used through TI provided API.
17-13DSEL1R/W0hInternal. Only to be used through TI provided API.
12-8DSEL0R/W0hInternal. Only to be used through TI provided API.
7-3CLKSELR/W0hSelect clock to output on DTB[0]
  • 0h = Select CLKULL (24 MHz during ACTIVE, 32kHz during STANDBY)
  • 1h = Select CLKSVT (48 MHz)
  • 2h = Select CLKADC (48 MHz)
  • 4h = Select tracking loop reference clock
  • 7h = Select LFCLK (selected by LFCLKSEL.MAIN)
  • Ah = Select HFOSC after qualification
  • Ch = Select HFXT divided by 8
  • Dh = Select HFXT
  • Eh = Select LFOSC
  • Fh = Select LFXT
  • 11h = Select AFOSC after qualification
  • 12h = HFOSC div by 2 clock
2-1RESERVEDR0hReserved
0ENR/W0hEnable DTB output

6.6.8.34 DTBCTL2 Register (Offset = 10Ch) [Reset = 00000000h]

DTBCTL2 is shown in Table 6-140.

Return to the Summary Table.

Digital test bus mux control

Table 6-140 DTBCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-10CLK2DTBSELR/W0hSelect a DTB other than DTB0 to route the clock. Value of 0 indicates that clock 2 won't be sent to DTB.
9-8RESERVEDR0hReserved
7-5CLKSEL2R/W0hSelect the clock that needs to be routed to a DTB other than DTB0
  • 0h = Select CLKULL (24 MHz during ACTIVE, 32kHz during STANDBY)
  • 1h = Select CLKSVT (48 MHz)
4-3RESERVEDR0hReserved
2-1CLK2DIVVALR/W0hThese bits are used to configure the divider value.
  • 0h = Divide by 2
  • 1h = Divide by 4
  • 2h = Divide by 8
  • 3h = Divide by 16
0CLK2DIVENR/W0hEnable divider on second clock path
  • 0h = Disable
  • 1h = Enable

6.6.8.35 TRIM0 Register (Offset = 110h) [Reset = 00000000h]

TRIM0 is shown in Table 6-141.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-141 TRIM0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25AFOSC_MODER/W0hInternal. Only to be used through TI provided API.
24-21AFOSC_MIDR/W0hInternal. Only to be used through TI provided API.
20-16AFOSC_COARSER/W0hInternal. Only to be used through TI provided API.
15-10RESERVEDR0hReserved
9HFOSC_MODER/W0hInternal. Only to be used through TI provided API.
8-5HFOSC_MIDR/W0hInternal. Only to be used through TI provided API.
4-0HFOSC_COARSER/W0hInternal. Only to be used through TI provided API.

6.6.8.36 TRIM1 Register (Offset = 114h) [Reset = 00000000h]

TRIM1 is shown in Table 6-142.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-142 TRIM1 Register Field Descriptions
BitFieldTypeResetDescription
31-30HFXTSLICERR/W0hInternal. Only to be used through TI provided API.
29-28PEAKIBIASR/W0hInternal. Only to be used through TI provided API.
27NABIAS_UDIGLDOR/W1hInternal. Only to be used through TI provided API.
26-24LDOBWR/W0hInternal. Only to be used through TI provided API.
23-20LDOFBR/W6hInternal. Only to be used through TI provided API.
19-16LFDLYR/WFhInternal. Only to be used through TI provided API.
15NABIAS_LFOSCR/W1hInternal. Only to be used through TI provided API.
14-8NABIAS_RESR/W14hInternal. Only to be used through TI provided API.
7-0LFOSC_CAPR/W39hInternal. Only to be used through TI provided API.

6.6.8.37 HFXTINIT Register (Offset = 118h) [Reset = 00000000h]

HFXTINIT is shown in Table 6-143.

Return to the Summary Table.

Initial values for HFXT ramping

Table 6-143 HFXTINIT Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-23AMPTHRR/W28hAmplitude threshold during HFXT ramping
22-16IDACR/W7FhInitial HFXT IDAC current
15-12IREFR/W8hInitial HFXT IREF current
11-6Q2CAPR/W0hInitial HFXT Q2 cap trim
  • 0h = Nominal 25C = 2.57E-12 F;Strong 25C = 1.50E-12 F;Weak 25C = 2.69E-12 F
  • 1h = Nominal 25C = 2.66E-12 F;Strong 25C = 1.60E-12 F;Weak 25C = 2.79E-12 F
  • 2h = Nominal 25C = 2.76E-12 F;Strong 25C = 1.69E-12 F;Weak 25C = 2.89E-12 F
  • 3h = Nominal 25C = 2.85E-12 F;Strong 25C = 1.79E-12 F;Weak 25C = 2.99E-12 F
  • 4h = Nominal 25C = 2.95E-12 F;Strong 25C = 1.89E-12 F;Weak 25C = 3.09E-12 F
  • 5h = Nominal 25C = 3.04E-12 F;Strong 25C = 1.99E-12 F;Weak 25C = 3.19E-12 F
  • 6h = Nominal 25C = 3.14E-12 F;Strong 25C = 2.09E-12 F;Weak 25C = 3.30E-12 F
  • 7h = Nominal 25C = 3.23E-12 F;Strong 25C = 2.19E-12 F;Weak 25C = 3.40E-12 F
  • 8h = Nominal 25C = 3.33E-12 F;Strong 25C = 2.29E-12 F;Weak 25C = 3.50E-12 F
  • 9h = Nominal 25C = 3.42E-12 F;Strong 25C = 2.39E-12 F;Weak 25C = 3.60E-12 F
  • Ah = Nominal 25C = 3.51E-12 F;Strong 25C = 2.49E-12 F;Weak 25C = 3.70E-12 F
  • Bh = Nominal 25C = 3.61E-12 F;Strong 25C = 2.59E-12 F;Weak 25C = 3.80E-12 F
  • Ch = Nominal 25C = 3.70E-12 F;Strong 25C = 2.69E-12 F;Weak 25C = 3.90E-12 F
  • Dh = Nominal 25C = 3.79E-12 F;Strong 25C = 2.79E-12 F;Weak 25C = 4.00E-12 F
  • Eh = Nominal 25C = 3.88E-12 F;Strong 25C = 2.89E-12 F;Weak 25C = 4.10E-12 F
  • Fh = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 10h = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 11h = Nominal 25C = 4.09E-12 F;Strong 25C = 3.11E-12 F;Weak 25C = 4.33E-12 F
  • 12h = Nominal 25C = 4.21E-12 F;Strong 25C = 3.23E-12 F;Weak 25C = 4.46E-12 F
  • 13h = Nominal 25C = 4.33E-12 F;Strong 25C = 3.36E-12 F;Weak 25C = 4.59E-12 F
  • 14h = Nominal 25C = 4.45E-12 F;Strong 25C = 3.48E-12 F;Weak 25C = 4.72E-12 F
  • 15h = Nominal 25C = 4.57E-12 F;Strong 25C = 3.60E-12 F;Weak 25C = 4.85E-12 F
  • 16h = Nominal 25C = 4.68E-12 F;Strong 25C = 3.73E-12 F;Weak 25C = 4.98E-12 F
  • 17h = Nominal 25C = 4.80E-12 F;Strong 25C = 3.85E-12 F;Weak 25C = 5.10E-12 F
  • 18h = Nominal 25C = 4.91E-12 F;Strong 25C = 3.97E-12 F;Weak 25C = 5.23E-12 F
  • 19h = Nominal 25C = 5.03E-12 F;Strong 25C = 4.09E-12 F;Weak 25C = 5.36E-12 F
  • 1Ah = Nominal 25C = 5.15E-12 F;Strong 25C = 4.21E-12 F;Weak 25C = 5.49E-12 F
  • 1Bh = Nominal 25C = 5.26E-12 F;Strong 25C = 4.32E-12 F;Weak 25C = 5.61E-12 F
  • 1Ch = Nominal 25C = 5.37E-12 F;Strong 25C = 4.44E-12 F;Weak 25C = 5.74E-12 F
  • 1Dh = Nominal 25C = 5.49E-12 F;Strong 25C = 4.56E-12 F;Weak 25C = 5.87E-12 F
  • 1Eh = Nominal 25C = 5.60E-12 F;Strong 25C = 4.67E-12 F;Weak 25C = 5.99E-12 F
  • 1Fh = Nominal 25C = 5.72E-12 F;Strong 25C = 4.79E-12 F;Weak 25C = 6.12E-12 F
  • 20h = Nominal 25C = 5.97E-12 F;Strong 25C = 5.05E-12 F;Weak 25C = 6.40E-12 F
  • 21h = Nominal 25C = 6.12E-12 F;Strong 25C = 5.20E-12 F;Weak 25C = 6.56E-12 F
  • 22h = Nominal 25C = 6.26E-12 F;Strong 25C = 5.35E-12 F;Weak 25C = 6.72E-12 F
  • 23h = Nominal 25C = 6.41E-12 F;Strong 25C = 5.49E-12 F;Weak 25C = 6.88E-12 F
  • 24h = Nominal 25C = 6.55E-12 F;Strong 25C = 5.63E-12 F;Weak 25C = 7.04E-12 F
  • 25h = Nominal 25C = 6.69E-12 F;Strong 25C = 5.78E-12 F;Weak 25C = 7.20E-12 F
  • 26h = Nominal 25C = 6.84E-12 F;Strong 25C = 5.92E-12 F;Weak 25C = 7.35E-12 F
  • 27h = Nominal 25C = 6.98E-12 F;Strong 25C = 6.06E-12 F;Weak 25C = 7.51E-12 F
  • 28h = Nominal 25C = 7.12E-12 F;Strong 25C = 6.21E-12 F;Weak 25C = 7.67E-12 F
  • 29h = Nominal 25C = 7.26E-12 F;Strong 25C = 6.35E-12 F;Weak 25C = 7.82E-12 F
  • 2Ah = Nominal 25C = 7.40E-12 F;Strong 25C = 6.49E-12 F;Weak 25C = 7.98E-12 F
  • 2Bh = Nominal 25C = 7.55E-12 F;Strong 25C = 6.63E-12 F;Weak 25C = 8.13E-12 F
  • 2Ch = Nominal 25C = 7.69E-12 F;Strong 25C = 6.77E-12 F;Weak 25C = 8.29E-12 F
  • 2Dh = Nominal 25C = 7.83E-12 F;Strong 25C = 6.91E-12 F;Weak 25C = 8.44E-12 F
  • 2Eh = Nominal 25C = 7.97E-12 F;Strong 25C = 7.05E-12 F;Weak 25C = 8.60E-12 F
  • 2Fh = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 30h = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 31h = Nominal 25C = 8.30E-12 F;Strong 25C = 7.38E-12 F;Weak 25C = 8.96E-12 F
  • 32h = Nominal 25C = 8.49E-12 F;Strong 25C = 7.57E-12 F;Weak 25C = 9.18E-12 F
  • 33h = Nominal 25C = 8.69E-12 F;Strong 25C = 7.76E-12 F;Weak 25C = 9.39E-12 F
  • 34h = Nominal 25C = 8.88E-12 F;Strong 25C = 7.94E-12 F;Weak 25C = 9.60E-12 F
  • 35h = Nominal 25C = 9.07E-12 F;Strong 25C = 8.13E-12 F;Weak 25C = 9.81E-12 F
  • 36h = Nominal 25C = 9.26E-12 F;Strong 25C = 8.32E-12 F;Weak 25C = 1.00E-11 F
  • 37h = Nominal 25C = 9.46E-12 F;Strong 25C = 8.51E-12 F;Weak 25C = 1.02E-11 F
  • 38h = Nominal 25C = 9.65E-12 F;Strong 25C = 8.70E-12 F;Weak 25C = 1.04E-11 F
  • 39h = Nominal 25C = 9.84E-12 F;Strong 25C = 8.89E-12 F;Weak 25C = 1.07E-11 F
  • 3Ah = Nominal 25C = 1.00E-11 F;Strong 25C = 9.07E-12 F;Weak 25C = 1.09E-11 F
  • 3Bh = Nominal 25C = 1.02E-11 F;Strong 25C = 9.26E-12 F;Weak 25C = 1.11E-11 F
  • 3Ch = Nominal 25C = 1.04E-11 F;Strong 25C = 9.45E-12 F;Weak 25C = 1.13E-11 F
  • 3Dh = Nominal 25C = 1.06E-11 F;Strong 25C = 9.64E-12 F;Weak 25C = 1.15E-11 F
  • 3Eh = Nominal 25C = 1.08E-11 F;Strong 25C = 9.82E-12 F;Weak 25C = 1.17E-11 F
  • 3Fh = Nominal 25C = 1.10E-11 F;Strong 25C = 1.00E-11 F;Weak 25C = 1.19E-11 F
5-0Q1CAPR/W0hInitial HFXT Q1 cap trim
  • 0h = Nominal 25C = 2.57E-12 F;Strong 25C = 1.50E-12 F;Weak 25C = 2.69E-12 F
  • 1h = Nominal 25C = 2.66E-12 F;Strong 25C = 1.60E-12 F;Weak 25C = 2.79E-12 F
  • 2h = Nominal 25C = 2.76E-12 F;Strong 25C = 1.69E-12 F;Weak 25C = 2.89E-12 F
  • 3h = Nominal 25C = 2.85E-12 F;Strong 25C = 1.79E-12 F;Weak 25C = 2.99E-12 F
  • 4h = Nominal 25C = 2.95E-12 F;Strong 25C = 1.89E-12 F;Weak 25C = 3.09E-12 F
  • 5h = Nominal 25C = 3.04E-12 F;Strong 25C = 1.99E-12 F;Weak 25C = 3.19E-12 F
  • 6h = Nominal 25C = 3.14E-12 F;Strong 25C = 2.09E-12 F;Weak 25C = 3.30E-12 F
  • 7h = Nominal 25C = 3.23E-12 F;Strong 25C = 2.19E-12 F;Weak 25C = 3.40E-12 F
  • 8h = Nominal 25C = 3.33E-12 F;Strong 25C = 2.29E-12 F;Weak 25C = 3.50E-12 F
  • 9h = Nominal 25C = 3.42E-12 F;Strong 25C = 2.39E-12 F;Weak 25C = 3.60E-12 F
  • Ah = Nominal 25C = 3.51E-12 F;Strong 25C = 2.49E-12 F;Weak 25C = 3.70E-12 F
  • Bh = Nominal 25C = 3.61E-12 F;Strong 25C = 2.59E-12 F;Weak 25C = 3.80E-12 F
  • Ch = Nominal 25C = 3.70E-12 F;Strong 25C = 2.69E-12 F;Weak 25C = 3.90E-12 F
  • Dh = Nominal 25C = 3.79E-12 F;Strong 25C = 2.79E-12 F;Weak 25C = 4.00E-12 F
  • Eh = Nominal 25C = 3.88E-12 F;Strong 25C = 2.89E-12 F;Weak 25C = 4.10E-12 F
  • Fh = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 10h = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 11h = Nominal 25C = 4.09E-12 F;Strong 25C = 3.11E-12 F;Weak 25C = 4.33E-12 F
  • 12h = Nominal 25C = 4.21E-12 F;Strong 25C = 3.23E-12 F;Weak 25C = 4.46E-12 F
  • 13h = Nominal 25C = 4.33E-12 F;Strong 25C = 3.36E-12 F;Weak 25C = 4.59E-12 F
  • 14h = Nominal 25C = 4.45E-12 F;Strong 25C = 3.48E-12 F;Weak 25C = 4.72E-12 F
  • 15h = Nominal 25C = 4.57E-12 F;Strong 25C = 3.60E-12 F;Weak 25C = 4.85E-12 F
  • 16h = Nominal 25C = 4.68E-12 F;Strong 25C = 3.73E-12 F;Weak 25C = 4.98E-12 F
  • 17h = Nominal 25C = 4.80E-12 F;Strong 25C = 3.85E-12 F;Weak 25C = 5.10E-12 F
  • 18h = Nominal 25C = 4.91E-12 F;Strong 25C = 3.97E-12 F;Weak 25C = 5.23E-12 F
  • 19h = Nominal 25C = 5.03E-12 F;Strong 25C = 4.09E-12 F;Weak 25C = 5.36E-12 F
  • 1Ah = Nominal 25C = 5.15E-12 F;Strong 25C = 4.21E-12 F;Weak 25C = 5.49E-12 F
  • 1Bh = Nominal 25C = 5.26E-12 F;Strong 25C = 4.32E-12 F;Weak 25C = 5.61E-12 F
  • 1Ch = Nominal 25C = 5.37E-12 F;Strong 25C = 4.44E-12 F;Weak 25C = 5.74E-12 F
  • 1Dh = Nominal 25C = 5.49E-12 F;Strong 25C = 4.56E-12 F;Weak 25C = 5.87E-12 F
  • 1Eh = Nominal 25C = 5.60E-12 F;Strong 25C = 4.67E-12 F;Weak 25C = 5.99E-12 F
  • 1Fh = Nominal 25C = 5.72E-12 F;Strong 25C = 4.79E-12 F;Weak 25C = 6.12E-12 F
  • 20h = Nominal 25C = 5.97E-12 F;Strong 25C = 5.05E-12 F;Weak 25C = 6.40E-12 F
  • 21h = Nominal 25C = 6.12E-12 F;Strong 25C = 5.20E-12 F;Weak 25C = 6.56E-12 F
  • 22h = Nominal 25C = 6.26E-12 F;Strong 25C = 5.35E-12 F;Weak 25C = 6.72E-12 F
  • 23h = Nominal 25C = 6.41E-12 F;Strong 25C = 5.49E-12 F;Weak 25C = 6.88E-12 F
  • 24h = Nominal 25C = 6.55E-12 F;Strong 25C = 5.63E-12 F;Weak 25C = 7.04E-12 F
  • 25h = Nominal 25C = 6.69E-12 F;Strong 25C = 5.78E-12 F;Weak 25C = 7.20E-12 F
  • 26h = Nominal 25C = 6.84E-12 F;Strong 25C = 5.92E-12 F;Weak 25C = 7.35E-12 F
  • 27h = Nominal 25C = 6.98E-12 F;Strong 25C = 6.06E-12 F;Weak 25C = 7.51E-12 F
  • 28h = Nominal 25C = 7.12E-12 F;Strong 25C = 6.21E-12 F;Weak 25C = 7.67E-12 F
  • 29h = Nominal 25C = 7.26E-12 F;Strong 25C = 6.35E-12 F;Weak 25C = 7.82E-12 F
  • 2Ah = Nominal 25C = 7.40E-12 F;Strong 25C = 6.49E-12 F;Weak 25C = 7.98E-12 F
  • 2Bh = Nominal 25C = 7.55E-12 F;Strong 25C = 6.63E-12 F;Weak 25C = 8.13E-12 F
  • 2Ch = Nominal 25C = 7.69E-12 F;Strong 25C = 6.77E-12 F;Weak 25C = 8.29E-12 F
  • 2Dh = Nominal 25C = 7.83E-12 F;Strong 25C = 6.91E-12 F;Weak 25C = 8.44E-12 F
  • 2Eh = Nominal 25C = 7.97E-12 F;Strong 25C = 7.05E-12 F;Weak 25C = 8.60E-12 F
  • 2Fh = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 30h = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 31h = Nominal 25C = 8.30E-12 F;Strong 25C = 7.38E-12 F;Weak 25C = 8.96E-12 F
  • 32h = Nominal 25C = 8.49E-12 F;Strong 25C = 7.57E-12 F;Weak 25C = 9.18E-12 F
  • 33h = Nominal 25C = 8.69E-12 F;Strong 25C = 7.76E-12 F;Weak 25C = 9.39E-12 F
  • 34h = Nominal 25C = 8.88E-12 F;Strong 25C = 7.94E-12 F;Weak 25C = 9.60E-12 F
  • 35h = Nominal 25C = 9.07E-12 F;Strong 25C = 8.13E-12 F;Weak 25C = 9.81E-12 F
  • 36h = Nominal 25C = 9.26E-12 F;Strong 25C = 8.32E-12 F;Weak 25C = 1.00E-11 F
  • 37h = Nominal 25C = 9.46E-12 F;Strong 25C = 8.51E-12 F;Weak 25C = 1.02E-11 F
  • 38h = Nominal 25C = 9.65E-12 F;Strong 25C = 8.70E-12 F;Weak 25C = 1.04E-11 F
  • 39h = Nominal 25C = 9.84E-12 F;Strong 25C = 8.89E-12 F;Weak 25C = 1.07E-11 F
  • 3Ah = Nominal 25C = 1.00E-11 F;Strong 25C = 9.07E-12 F;Weak 25C = 1.09E-11 F
  • 3Bh = Nominal 25C = 1.02E-11 F;Strong 25C = 9.26E-12 F;Weak 25C = 1.11E-11 F
  • 3Ch = Nominal 25C = 1.04E-11 F;Strong 25C = 9.45E-12 F;Weak 25C = 1.13E-11 F
  • 3Dh = Nominal 25C = 1.06E-11 F;Strong 25C = 9.64E-12 F;Weak 25C = 1.15E-11 F
  • 3Eh = Nominal 25C = 1.08E-11 F;Strong 25C = 9.82E-12 F;Weak 25C = 1.17E-11 F
  • 3Fh = Nominal 25C = 1.10E-11 F;Strong 25C = 1.00E-11 F;Weak 25C = 1.19E-11 F

6.6.8.38 HFXTTARG Register (Offset = 11Ch) [Reset = 00000000h]

HFXTTARG is shown in Table 6-144.

Return to the Summary Table.

Target values for HFXT ramping

Table 6-144 HFXTTARG Register Field Descriptions
BitFieldTypeResetDescription
31-30AMPHYSTR/W1hADC hysteresis used during IDAC updates.
Every AMPCFG1.INTERVAL, IDAC will be regulated
- up as long as ADC < AMPTHR
- down as long as ADC > AMPTHR+AMPHYST
29-23AMPTHRR/W28hMinimum HFXT amplitude
22-16IDACR/W46hMinimum IDAC current
15-12IREFR/W4hTarget HFXT IREF current
11-6Q2CAPR/W2DhTarget HFXT Q2 cap trim
  • 0h = Nominal 25C = 2.57E-12 F;Strong 25C = 1.50E-12 F;Weak 25C = 2.69E-12 F
  • 1h = Nominal 25C = 2.66E-12 F;Strong 25C = 1.60E-12 F;Weak 25C = 2.79E-12 F
  • 2h = Nominal 25C = 2.76E-12 F;Strong 25C = 1.69E-12 F;Weak 25C = 2.89E-12 F
  • 3h = Nominal 25C = 2.85E-12 F;Strong 25C = 1.79E-12 F;Weak 25C = 2.99E-12 F
  • 4h = Nominal 25C = 2.95E-12 F;Strong 25C = 1.89E-12 F;Weak 25C = 3.09E-12 F
  • 5h = Nominal 25C = 3.04E-12 F;Strong 25C = 1.99E-12 F;Weak 25C = 3.19E-12 F
  • 6h = Nominal 25C = 3.14E-12 F;Strong 25C = 2.09E-12 F;Weak 25C = 3.30E-12 F
  • 7h = Nominal 25C = 3.23E-12 F;Strong 25C = 2.19E-12 F;Weak 25C = 3.40E-12 F
  • 8h = Nominal 25C = 3.33E-12 F;Strong 25C = 2.29E-12 F;Weak 25C = 3.50E-12 F
  • 9h = Nominal 25C = 3.42E-12 F;Strong 25C = 2.39E-12 F;Weak 25C = 3.60E-12 F
  • Ah = Nominal 25C = 3.51E-12 F;Strong 25C = 2.49E-12 F;Weak 25C = 3.70E-12 F
  • Bh = Nominal 25C = 3.61E-12 F;Strong 25C = 2.59E-12 F;Weak 25C = 3.80E-12 F
  • Ch = Nominal 25C = 3.70E-12 F;Strong 25C = 2.69E-12 F;Weak 25C = 3.90E-12 F
  • Dh = Nominal 25C = 3.79E-12 F;Strong 25C = 2.79E-12 F;Weak 25C = 4.00E-12 F
  • Eh = Nominal 25C = 3.88E-12 F;Strong 25C = 2.89E-12 F;Weak 25C = 4.10E-12 F
  • Fh = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 10h = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 11h = Nominal 25C = 4.09E-12 F;Strong 25C = 3.11E-12 F;Weak 25C = 4.33E-12 F
  • 12h = Nominal 25C = 4.21E-12 F;Strong 25C = 3.23E-12 F;Weak 25C = 4.46E-12 F
  • 13h = Nominal 25C = 4.33E-12 F;Strong 25C = 3.36E-12 F;Weak 25C = 4.59E-12 F
  • 14h = Nominal 25C = 4.45E-12 F;Strong 25C = 3.48E-12 F;Weak 25C = 4.72E-12 F
  • 15h = Nominal 25C = 4.57E-12 F;Strong 25C = 3.60E-12 F;Weak 25C = 4.85E-12 F
  • 16h = Nominal 25C = 4.68E-12 F;Strong 25C = 3.73E-12 F;Weak 25C = 4.98E-12 F
  • 17h = Nominal 25C = 4.80E-12 F;Strong 25C = 3.85E-12 F;Weak 25C = 5.10E-12 F
  • 18h = Nominal 25C = 4.91E-12 F;Strong 25C = 3.97E-12 F;Weak 25C = 5.23E-12 F
  • 19h = Nominal 25C = 5.03E-12 F;Strong 25C = 4.09E-12 F;Weak 25C = 5.36E-12 F
  • 1Ah = Nominal 25C = 5.15E-12 F;Strong 25C = 4.21E-12 F;Weak 25C = 5.49E-12 F
  • 1Bh = Nominal 25C = 5.26E-12 F;Strong 25C = 4.32E-12 F;Weak 25C = 5.61E-12 F
  • 1Ch = Nominal 25C = 5.37E-12 F;Strong 25C = 4.44E-12 F;Weak 25C = 5.74E-12 F
  • 1Dh = Nominal 25C = 5.49E-12 F;Strong 25C = 4.56E-12 F;Weak 25C = 5.87E-12 F
  • 1Eh = Nominal 25C = 5.60E-12 F;Strong 25C = 4.67E-12 F;Weak 25C = 5.99E-12 F
  • 1Fh = Nominal 25C = 5.72E-12 F;Strong 25C = 4.79E-12 F;Weak 25C = 6.12E-12 F
  • 20h = Nominal 25C = 5.97E-12 F;Strong 25C = 5.05E-12 F;Weak 25C = 6.40E-12 F
  • 21h = Nominal 25C = 6.12E-12 F;Strong 25C = 5.20E-12 F;Weak 25C = 6.56E-12 F
  • 22h = Nominal 25C = 6.26E-12 F;Strong 25C = 5.35E-12 F;Weak 25C = 6.72E-12 F
  • 23h = Nominal 25C = 6.41E-12 F;Strong 25C = 5.49E-12 F;Weak 25C = 6.88E-12 F
  • 24h = Nominal 25C = 6.55E-12 F;Strong 25C = 5.63E-12 F;Weak 25C = 7.04E-12 F
  • 25h = Nominal 25C = 6.69E-12 F;Strong 25C = 5.78E-12 F;Weak 25C = 7.20E-12 F
  • 26h = Nominal 25C = 6.84E-12 F;Strong 25C = 5.92E-12 F;Weak 25C = 7.35E-12 F
  • 27h = Nominal 25C = 6.98E-12 F;Strong 25C = 6.06E-12 F;Weak 25C = 7.51E-12 F
  • 28h = Nominal 25C = 7.12E-12 F;Strong 25C = 6.21E-12 F;Weak 25C = 7.67E-12 F
  • 29h = Nominal 25C = 7.26E-12 F;Strong 25C = 6.35E-12 F;Weak 25C = 7.82E-12 F
  • 2Ah = Nominal 25C = 7.40E-12 F;Strong 25C = 6.49E-12 F;Weak 25C = 7.98E-12 F
  • 2Bh = Nominal 25C = 7.55E-12 F;Strong 25C = 6.63E-12 F;Weak 25C = 8.13E-12 F
  • 2Ch = Nominal 25C = 7.69E-12 F;Strong 25C = 6.77E-12 F;Weak 25C = 8.29E-12 F
  • 2Dh = Nominal 25C = 7.83E-12 F;Strong 25C = 6.91E-12 F;Weak 25C = 8.44E-12 F
  • 2Eh = Nominal 25C = 7.97E-12 F;Strong 25C = 7.05E-12 F;Weak 25C = 8.60E-12 F
  • 2Fh = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 30h = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 31h = Nominal 25C = 8.30E-12 F;Strong 25C = 7.38E-12 F;Weak 25C = 8.96E-12 F
  • 32h = Nominal 25C = 8.49E-12 F;Strong 25C = 7.57E-12 F;Weak 25C = 9.18E-12 F
  • 33h = Nominal 25C = 8.69E-12 F;Strong 25C = 7.76E-12 F;Weak 25C = 9.39E-12 F
  • 34h = Nominal 25C = 8.88E-12 F;Strong 25C = 7.94E-12 F;Weak 25C = 9.60E-12 F
  • 35h = Nominal 25C = 9.07E-12 F;Strong 25C = 8.13E-12 F;Weak 25C = 9.81E-12 F
  • 36h = Nominal 25C = 9.26E-12 F;Strong 25C = 8.32E-12 F;Weak 25C = 1.00E-11 F
  • 37h = Nominal 25C = 9.46E-12 F;Strong 25C = 8.51E-12 F;Weak 25C = 1.02E-11 F
  • 38h = Nominal 25C = 9.65E-12 F;Strong 25C = 8.70E-12 F;Weak 25C = 1.04E-11 F
  • 39h = Nominal 25C = 9.84E-12 F;Strong 25C = 8.89E-12 F;Weak 25C = 1.07E-11 F
  • 3Ah = Nominal 25C = 1.00E-11 F;Strong 25C = 9.07E-12 F;Weak 25C = 1.09E-11 F
  • 3Bh = Nominal 25C = 1.02E-11 F;Strong 25C = 9.26E-12 F;Weak 25C = 1.11E-11 F
  • 3Ch = Nominal 25C = 1.04E-11 F;Strong 25C = 9.45E-12 F;Weak 25C = 1.13E-11 F
  • 3Dh = Nominal 25C = 1.06E-11 F;Strong 25C = 9.64E-12 F;Weak 25C = 1.15E-11 F
  • 3Eh = Nominal 25C = 1.08E-11 F;Strong 25C = 9.82E-12 F;Weak 25C = 1.17E-11 F
  • 3Fh = Nominal 25C = 1.10E-11 F;Strong 25C = 1.00E-11 F;Weak 25C = 1.19E-11 F
5-0Q1CAPR/W2DhTarget HFXT Q1 cap trim
  • 0h = Nominal 25C = 2.57E-12 F;Strong 25C = 1.50E-12 F;Weak 25C = 2.69E-12 F
  • 1h = Nominal 25C = 2.66E-12 F;Strong 25C = 1.60E-12 F;Weak 25C = 2.79E-12 F
  • 2h = Nominal 25C = 2.76E-12 F;Strong 25C = 1.69E-12 F;Weak 25C = 2.89E-12 F
  • 3h = Nominal 25C = 2.85E-12 F;Strong 25C = 1.79E-12 F;Weak 25C = 2.99E-12 F
  • 4h = Nominal 25C = 2.95E-12 F;Strong 25C = 1.89E-12 F;Weak 25C = 3.09E-12 F
  • 5h = Nominal 25C = 3.04E-12 F;Strong 25C = 1.99E-12 F;Weak 25C = 3.19E-12 F
  • 6h = Nominal 25C = 3.14E-12 F;Strong 25C = 2.09E-12 F;Weak 25C = 3.30E-12 F
  • 7h = Nominal 25C = 3.23E-12 F;Strong 25C = 2.19E-12 F;Weak 25C = 3.40E-12 F
  • 8h = Nominal 25C = 3.33E-12 F;Strong 25C = 2.29E-12 F;Weak 25C = 3.50E-12 F
  • 9h = Nominal 25C = 3.42E-12 F;Strong 25C = 2.39E-12 F;Weak 25C = 3.60E-12 F
  • Ah = Nominal 25C = 3.51E-12 F;Strong 25C = 2.49E-12 F;Weak 25C = 3.70E-12 F
  • Bh = Nominal 25C = 3.61E-12 F;Strong 25C = 2.59E-12 F;Weak 25C = 3.80E-12 F
  • Ch = Nominal 25C = 3.70E-12 F;Strong 25C = 2.69E-12 F;Weak 25C = 3.90E-12 F
  • Dh = Nominal 25C = 3.79E-12 F;Strong 25C = 2.79E-12 F;Weak 25C = 4.00E-12 F
  • Eh = Nominal 25C = 3.88E-12 F;Strong 25C = 2.89E-12 F;Weak 25C = 4.10E-12 F
  • Fh = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 10h = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 11h = Nominal 25C = 4.09E-12 F;Strong 25C = 3.11E-12 F;Weak 25C = 4.33E-12 F
  • 12h = Nominal 25C = 4.21E-12 F;Strong 25C = 3.23E-12 F;Weak 25C = 4.46E-12 F
  • 13h = Nominal 25C = 4.33E-12 F;Strong 25C = 3.36E-12 F;Weak 25C = 4.59E-12 F
  • 14h = Nominal 25C = 4.45E-12 F;Strong 25C = 3.48E-12 F;Weak 25C = 4.72E-12 F
  • 15h = Nominal 25C = 4.57E-12 F;Strong 25C = 3.60E-12 F;Weak 25C = 4.85E-12 F
  • 16h = Nominal 25C = 4.68E-12 F;Strong 25C = 3.73E-12 F;Weak 25C = 4.98E-12 F
  • 17h = Nominal 25C = 4.80E-12 F;Strong 25C = 3.85E-12 F;Weak 25C = 5.10E-12 F
  • 18h = Nominal 25C = 4.91E-12 F;Strong 25C = 3.97E-12 F;Weak 25C = 5.23E-12 F
  • 19h = Nominal 25C = 5.03E-12 F;Strong 25C = 4.09E-12 F;Weak 25C = 5.36E-12 F
  • 1Ah = Nominal 25C = 5.15E-12 F;Strong 25C = 4.21E-12 F;Weak 25C = 5.49E-12 F
  • 1Bh = Nominal 25C = 5.26E-12 F;Strong 25C = 4.32E-12 F;Weak 25C = 5.61E-12 F
  • 1Ch = Nominal 25C = 5.37E-12 F;Strong 25C = 4.44E-12 F;Weak 25C = 5.74E-12 F
  • 1Dh = Nominal 25C = 5.49E-12 F;Strong 25C = 4.56E-12 F;Weak 25C = 5.87E-12 F
  • 1Eh = Nominal 25C = 5.60E-12 F;Strong 25C = 4.67E-12 F;Weak 25C = 5.99E-12 F
  • 1Fh = Nominal 25C = 5.72E-12 F;Strong 25C = 4.79E-12 F;Weak 25C = 6.12E-12 F
  • 20h = Nominal 25C = 5.97E-12 F;Strong 25C = 5.05E-12 F;Weak 25C = 6.40E-12 F
  • 21h = Nominal 25C = 6.12E-12 F;Strong 25C = 5.20E-12 F;Weak 25C = 6.56E-12 F
  • 22h = Nominal 25C = 6.26E-12 F;Strong 25C = 5.35E-12 F;Weak 25C = 6.72E-12 F
  • 23h = Nominal 25C = 6.41E-12 F;Strong 25C = 5.49E-12 F;Weak 25C = 6.88E-12 F
  • 24h = Nominal 25C = 6.55E-12 F;Strong 25C = 5.63E-12 F;Weak 25C = 7.04E-12 F
  • 25h = Nominal 25C = 6.69E-12 F;Strong 25C = 5.78E-12 F;Weak 25C = 7.20E-12 F
  • 26h = Nominal 25C = 6.84E-12 F;Strong 25C = 5.92E-12 F;Weak 25C = 7.35E-12 F
  • 27h = Nominal 25C = 6.98E-12 F;Strong 25C = 6.06E-12 F;Weak 25C = 7.51E-12 F
  • 28h = Nominal 25C = 7.12E-12 F;Strong 25C = 6.21E-12 F;Weak 25C = 7.67E-12 F
  • 29h = Nominal 25C = 7.26E-12 F;Strong 25C = 6.35E-12 F;Weak 25C = 7.82E-12 F
  • 2Ah = Nominal 25C = 7.40E-12 F;Strong 25C = 6.49E-12 F;Weak 25C = 7.98E-12 F
  • 2Bh = Nominal 25C = 7.55E-12 F;Strong 25C = 6.63E-12 F;Weak 25C = 8.13E-12 F
  • 2Ch = Nominal 25C = 7.69E-12 F;Strong 25C = 6.77E-12 F;Weak 25C = 8.29E-12 F
  • 2Dh = Nominal 25C = 7.83E-12 F;Strong 25C = 6.91E-12 F;Weak 25C = 8.44E-12 F
  • 2Eh = Nominal 25C = 7.97E-12 F;Strong 25C = 7.05E-12 F;Weak 25C = 8.60E-12 F
  • 2Fh = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 30h = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 31h = Nominal 25C = 8.30E-12 F;Strong 25C = 7.38E-12 F;Weak 25C = 8.96E-12 F
  • 32h = Nominal 25C = 8.49E-12 F;Strong 25C = 7.57E-12 F;Weak 25C = 9.18E-12 F
  • 33h = Nominal 25C = 8.69E-12 F;Strong 25C = 7.76E-12 F;Weak 25C = 9.39E-12 F
  • 34h = Nominal 25C = 8.88E-12 F;Strong 25C = 7.94E-12 F;Weak 25C = 9.60E-12 F
  • 35h = Nominal 25C = 9.07E-12 F;Strong 25C = 8.13E-12 F;Weak 25C = 9.81E-12 F
  • 36h = Nominal 25C = 9.26E-12 F;Strong 25C = 8.32E-12 F;Weak 25C = 1.00E-11 F
  • 37h = Nominal 25C = 9.46E-12 F;Strong 25C = 8.51E-12 F;Weak 25C = 1.02E-11 F
  • 38h = Nominal 25C = 9.65E-12 F;Strong 25C = 8.70E-12 F;Weak 25C = 1.04E-11 F
  • 39h = Nominal 25C = 9.84E-12 F;Strong 25C = 8.89E-12 F;Weak 25C = 1.07E-11 F
  • 3Ah = Nominal 25C = 1.00E-11 F;Strong 25C = 9.07E-12 F;Weak 25C = 1.09E-11 F
  • 3Bh = Nominal 25C = 1.02E-11 F;Strong 25C = 9.26E-12 F;Weak 25C = 1.11E-11 F
  • 3Ch = Nominal 25C = 1.04E-11 F;Strong 25C = 9.45E-12 F;Weak 25C = 1.13E-11 F
  • 3Dh = Nominal 25C = 1.06E-11 F;Strong 25C = 9.64E-12 F;Weak 25C = 1.15E-11 F
  • 3Eh = Nominal 25C = 1.08E-11 F;Strong 25C = 9.82E-12 F;Weak 25C = 1.17E-11 F
  • 3Fh = Nominal 25C = 1.10E-11 F;Strong 25C = 1.00E-11 F;Weak 25C = 1.19E-11 F

6.6.8.39 HFXTDYN Register (Offset = 120h) [Reset = 00000000h]

HFXTDYN is shown in Table 6-145.

Return to the Summary Table.

Alternative target values for HFXT configuration
Software can change these values to dynamically transition the HFXT configuration while HFXT is running.
Set SEL to select the alternative set of target values.

Table 6-145 HFXTDYN Register Field Descriptions
BitFieldTypeResetDescription
31SELR/W0hSelect the dynamic configuration.
Amplitude ramping will always happen using the values in HFXTINIT, and HFXTTARG.
Afterwards, this bit can be used to select between HFXTTARG and HFXTDYN.
Hardware will ensure a smooth transition of analog control signals.
  • 0h = Select configuration in CKM.HFXTTARG0 and CKM.HFXTTARG1.
  • 1h = Select configuration in CKM.HFXTDYN0 and CKM.HFXTDYN1.
30RESERVEDR0hReserved
29-23AMPTHRR/W28hMinimum HFXT amplitude
22-16IDACR/W46hMinimum IDAC current
15-12IREFR/W4hTarget HFXT IREF current
11-6Q2CAPR/W2DhTarget HFXT Q2 cap trim
  • 0h = Nominal 25C = 2.57E-12 F;Strong 25C = 1.50E-12 F;Weak 25C = 2.69E-12 F
  • 1h = Nominal 25C = 2.66E-12 F;Strong 25C = 1.60E-12 F;Weak 25C = 2.79E-12 F
  • 2h = Nominal 25C = 2.76E-12 F;Strong 25C = 1.69E-12 F;Weak 25C = 2.89E-12 F
  • 3h = Nominal 25C = 2.85E-12 F;Strong 25C = 1.79E-12 F;Weak 25C = 2.99E-12 F
  • 4h = Nominal 25C = 2.95E-12 F;Strong 25C = 1.89E-12 F;Weak 25C = 3.09E-12 F
  • 5h = Nominal 25C = 3.04E-12 F;Strong 25C = 1.99E-12 F;Weak 25C = 3.19E-12 F
  • 6h = Nominal 25C = 3.14E-12 F;Strong 25C = 2.09E-12 F;Weak 25C = 3.30E-12 F
  • 7h = Nominal 25C = 3.23E-12 F;Strong 25C = 2.19E-12 F;Weak 25C = 3.40E-12 F
  • 8h = Nominal 25C = 3.33E-12 F;Strong 25C = 2.29E-12 F;Weak 25C = 3.50E-12 F
  • 9h = Nominal 25C = 3.42E-12 F;Strong 25C = 2.39E-12 F;Weak 25C = 3.60E-12 F
  • Ah = Nominal 25C = 3.51E-12 F;Strong 25C = 2.49E-12 F;Weak 25C = 3.70E-12 F
  • Bh = Nominal 25C = 3.61E-12 F;Strong 25C = 2.59E-12 F;Weak 25C = 3.80E-12 F
  • Ch = Nominal 25C = 3.70E-12 F;Strong 25C = 2.69E-12 F;Weak 25C = 3.90E-12 F
  • Dh = Nominal 25C = 3.79E-12 F;Strong 25C = 2.79E-12 F;Weak 25C = 4.00E-12 F
  • Eh = Nominal 25C = 3.88E-12 F;Strong 25C = 2.89E-12 F;Weak 25C = 4.10E-12 F
  • Fh = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 10h = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 11h = Nominal 25C = 4.09E-12 F;Strong 25C = 3.11E-12 F;Weak 25C = 4.33E-12 F
  • 12h = Nominal 25C = 4.21E-12 F;Strong 25C = 3.23E-12 F;Weak 25C = 4.46E-12 F
  • 13h = Nominal 25C = 4.33E-12 F;Strong 25C = 3.36E-12 F;Weak 25C = 4.59E-12 F
  • 14h = Nominal 25C = 4.45E-12 F;Strong 25C = 3.48E-12 F;Weak 25C = 4.72E-12 F
  • 15h = Nominal 25C = 4.57E-12 F;Strong 25C = 3.60E-12 F;Weak 25C = 4.85E-12 F
  • 16h = Nominal 25C = 4.68E-12 F;Strong 25C = 3.73E-12 F;Weak 25C = 4.98E-12 F
  • 17h = Nominal 25C = 4.80E-12 F;Strong 25C = 3.85E-12 F;Weak 25C = 5.10E-12 F
  • 18h = Nominal 25C = 4.91E-12 F;Strong 25C = 3.97E-12 F;Weak 25C = 5.23E-12 F
  • 19h = Nominal 25C = 5.03E-12 F;Strong 25C = 4.09E-12 F;Weak 25C = 5.36E-12 F
  • 1Ah = Nominal 25C = 5.15E-12 F;Strong 25C = 4.21E-12 F;Weak 25C = 5.49E-12 F
  • 1Bh = Nominal 25C = 5.26E-12 F;Strong 25C = 4.32E-12 F;Weak 25C = 5.61E-12 F
  • 1Ch = Nominal 25C = 5.37E-12 F;Strong 25C = 4.44E-12 F;Weak 25C = 5.74E-12 F
  • 1Dh = Nominal 25C = 5.49E-12 F;Strong 25C = 4.56E-12 F;Weak 25C = 5.87E-12 F
  • 1Eh = Nominal 25C = 5.60E-12 F;Strong 25C = 4.67E-12 F;Weak 25C = 5.99E-12 F
  • 1Fh = Nominal 25C = 5.72E-12 F;Strong 25C = 4.79E-12 F;Weak 25C = 6.12E-12 F
  • 20h = Nominal 25C = 5.97E-12 F;Strong 25C = 5.05E-12 F;Weak 25C = 6.40E-12 F
  • 21h = Nominal 25C = 6.12E-12 F;Strong 25C = 5.20E-12 F;Weak 25C = 6.56E-12 F
  • 22h = Nominal 25C = 6.26E-12 F;Strong 25C = 5.35E-12 F;Weak 25C = 6.72E-12 F
  • 23h = Nominal 25C = 6.41E-12 F;Strong 25C = 5.49E-12 F;Weak 25C = 6.88E-12 F
  • 24h = Nominal 25C = 6.55E-12 F;Strong 25C = 5.63E-12 F;Weak 25C = 7.04E-12 F
  • 25h = Nominal 25C = 6.69E-12 F;Strong 25C = 5.78E-12 F;Weak 25C = 7.20E-12 F
  • 26h = Nominal 25C = 6.84E-12 F;Strong 25C = 5.92E-12 F;Weak 25C = 7.35E-12 F
  • 27h = Nominal 25C = 6.98E-12 F;Strong 25C = 6.06E-12 F;Weak 25C = 7.51E-12 F
  • 28h = Nominal 25C = 7.12E-12 F;Strong 25C = 6.21E-12 F;Weak 25C = 7.67E-12 F
  • 29h = Nominal 25C = 7.26E-12 F;Strong 25C = 6.35E-12 F;Weak 25C = 7.82E-12 F
  • 2Ah = Nominal 25C = 7.40E-12 F;Strong 25C = 6.49E-12 F;Weak 25C = 7.98E-12 F
  • 2Bh = Nominal 25C = 7.55E-12 F;Strong 25C = 6.63E-12 F;Weak 25C = 8.13E-12 F
  • 2Ch = Nominal 25C = 7.69E-12 F;Strong 25C = 6.77E-12 F;Weak 25C = 8.29E-12 F
  • 2Dh = Nominal 25C = 7.83E-12 F;Strong 25C = 6.91E-12 F;Weak 25C = 8.44E-12 F
  • 2Eh = Nominal 25C = 7.97E-12 F;Strong 25C = 7.05E-12 F;Weak 25C = 8.60E-12 F
  • 2Fh = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 30h = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 31h = Nominal 25C = 8.30E-12 F;Strong 25C = 7.38E-12 F;Weak 25C = 8.96E-12 F
  • 32h = Nominal 25C = 8.49E-12 F;Strong 25C = 7.57E-12 F;Weak 25C = 9.18E-12 F
  • 33h = Nominal 25C = 8.69E-12 F;Strong 25C = 7.76E-12 F;Weak 25C = 9.39E-12 F
  • 34h = Nominal 25C = 8.88E-12 F;Strong 25C = 7.94E-12 F;Weak 25C = 9.60E-12 F
  • 35h = Nominal 25C = 9.07E-12 F;Strong 25C = 8.13E-12 F;Weak 25C = 9.81E-12 F
  • 36h = Nominal 25C = 9.26E-12 F;Strong 25C = 8.32E-12 F;Weak 25C = 1.00E-11 F
  • 37h = Nominal 25C = 9.46E-12 F;Strong 25C = 8.51E-12 F;Weak 25C = 1.02E-11 F
  • 38h = Nominal 25C = 9.65E-12 F;Strong 25C = 8.70E-12 F;Weak 25C = 1.04E-11 F
  • 39h = Nominal 25C = 9.84E-12 F;Strong 25C = 8.89E-12 F;Weak 25C = 1.07E-11 F
  • 3Ah = Nominal 25C = 1.00E-11 F;Strong 25C = 9.07E-12 F;Weak 25C = 1.09E-11 F
  • 3Bh = Nominal 25C = 1.02E-11 F;Strong 25C = 9.26E-12 F;Weak 25C = 1.11E-11 F
  • 3Ch = Nominal 25C = 1.04E-11 F;Strong 25C = 9.45E-12 F;Weak 25C = 1.13E-11 F
  • 3Dh = Nominal 25C = 1.06E-11 F;Strong 25C = 9.64E-12 F;Weak 25C = 1.15E-11 F
  • 3Eh = Nominal 25C = 1.08E-11 F;Strong 25C = 9.82E-12 F;Weak 25C = 1.17E-11 F
  • 3Fh = Nominal 25C = 1.10E-11 F;Strong 25C = 1.00E-11 F;Weak 25C = 1.19E-11 F
5-0Q1CAPR/W2DhTarget HFXT Q1 cap trim
  • 0h = Nominal 25C = 2.57E-12 F;Strong 25C = 1.50E-12 F;Weak 25C = 2.69E-12 F
  • 1h = Nominal 25C = 2.66E-12 F;Strong 25C = 1.60E-12 F;Weak 25C = 2.79E-12 F
  • 2h = Nominal 25C = 2.76E-12 F;Strong 25C = 1.69E-12 F;Weak 25C = 2.89E-12 F
  • 3h = Nominal 25C = 2.85E-12 F;Strong 25C = 1.79E-12 F;Weak 25C = 2.99E-12 F
  • 4h = Nominal 25C = 2.95E-12 F;Strong 25C = 1.89E-12 F;Weak 25C = 3.09E-12 F
  • 5h = Nominal 25C = 3.04E-12 F;Strong 25C = 1.99E-12 F;Weak 25C = 3.19E-12 F
  • 6h = Nominal 25C = 3.14E-12 F;Strong 25C = 2.09E-12 F;Weak 25C = 3.30E-12 F
  • 7h = Nominal 25C = 3.23E-12 F;Strong 25C = 2.19E-12 F;Weak 25C = 3.40E-12 F
  • 8h = Nominal 25C = 3.33E-12 F;Strong 25C = 2.29E-12 F;Weak 25C = 3.50E-12 F
  • 9h = Nominal 25C = 3.42E-12 F;Strong 25C = 2.39E-12 F;Weak 25C = 3.60E-12 F
  • Ah = Nominal 25C = 3.51E-12 F;Strong 25C = 2.49E-12 F;Weak 25C = 3.70E-12 F
  • Bh = Nominal 25C = 3.61E-12 F;Strong 25C = 2.59E-12 F;Weak 25C = 3.80E-12 F
  • Ch = Nominal 25C = 3.70E-12 F;Strong 25C = 2.69E-12 F;Weak 25C = 3.90E-12 F
  • Dh = Nominal 25C = 3.79E-12 F;Strong 25C = 2.79E-12 F;Weak 25C = 4.00E-12 F
  • Eh = Nominal 25C = 3.88E-12 F;Strong 25C = 2.89E-12 F;Weak 25C = 4.10E-12 F
  • Fh = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 10h = Nominal 25C = 3.97E-12 F;Strong 25C = 2.98E-12 F;Weak 25C = 4.20E-12 F
  • 11h = Nominal 25C = 4.09E-12 F;Strong 25C = 3.11E-12 F;Weak 25C = 4.33E-12 F
  • 12h = Nominal 25C = 4.21E-12 F;Strong 25C = 3.23E-12 F;Weak 25C = 4.46E-12 F
  • 13h = Nominal 25C = 4.33E-12 F;Strong 25C = 3.36E-12 F;Weak 25C = 4.59E-12 F
  • 14h = Nominal 25C = 4.45E-12 F;Strong 25C = 3.48E-12 F;Weak 25C = 4.72E-12 F
  • 15h = Nominal 25C = 4.57E-12 F;Strong 25C = 3.60E-12 F;Weak 25C = 4.85E-12 F
  • 16h = Nominal 25C = 4.68E-12 F;Strong 25C = 3.73E-12 F;Weak 25C = 4.98E-12 F
  • 17h = Nominal 25C = 4.80E-12 F;Strong 25C = 3.85E-12 F;Weak 25C = 5.10E-12 F
  • 18h = Nominal 25C = 4.91E-12 F;Strong 25C = 3.97E-12 F;Weak 25C = 5.23E-12 F
  • 19h = Nominal 25C = 5.03E-12 F;Strong 25C = 4.09E-12 F;Weak 25C = 5.36E-12 F
  • 1Ah = Nominal 25C = 5.15E-12 F;Strong 25C = 4.21E-12 F;Weak 25C = 5.49E-12 F
  • 1Bh = Nominal 25C = 5.26E-12 F;Strong 25C = 4.32E-12 F;Weak 25C = 5.61E-12 F
  • 1Ch = Nominal 25C = 5.37E-12 F;Strong 25C = 4.44E-12 F;Weak 25C = 5.74E-12 F
  • 1Dh = Nominal 25C = 5.49E-12 F;Strong 25C = 4.56E-12 F;Weak 25C = 5.87E-12 F
  • 1Eh = Nominal 25C = 5.60E-12 F;Strong 25C = 4.67E-12 F;Weak 25C = 5.99E-12 F
  • 1Fh = Nominal 25C = 5.72E-12 F;Strong 25C = 4.79E-12 F;Weak 25C = 6.12E-12 F
  • 20h = Nominal 25C = 5.97E-12 F;Strong 25C = 5.05E-12 F;Weak 25C = 6.40E-12 F
  • 21h = Nominal 25C = 6.12E-12 F;Strong 25C = 5.20E-12 F;Weak 25C = 6.56E-12 F
  • 22h = Nominal 25C = 6.26E-12 F;Strong 25C = 5.35E-12 F;Weak 25C = 6.72E-12 F
  • 23h = Nominal 25C = 6.41E-12 F;Strong 25C = 5.49E-12 F;Weak 25C = 6.88E-12 F
  • 24h = Nominal 25C = 6.55E-12 F;Strong 25C = 5.63E-12 F;Weak 25C = 7.04E-12 F
  • 25h = Nominal 25C = 6.69E-12 F;Strong 25C = 5.78E-12 F;Weak 25C = 7.20E-12 F
  • 26h = Nominal 25C = 6.84E-12 F;Strong 25C = 5.92E-12 F;Weak 25C = 7.35E-12 F
  • 27h = Nominal 25C = 6.98E-12 F;Strong 25C = 6.06E-12 F;Weak 25C = 7.51E-12 F
  • 28h = Nominal 25C = 7.12E-12 F;Strong 25C = 6.21E-12 F;Weak 25C = 7.67E-12 F
  • 29h = Nominal 25C = 7.26E-12 F;Strong 25C = 6.35E-12 F;Weak 25C = 7.82E-12 F
  • 2Ah = Nominal 25C = 7.40E-12 F;Strong 25C = 6.49E-12 F;Weak 25C = 7.98E-12 F
  • 2Bh = Nominal 25C = 7.55E-12 F;Strong 25C = 6.63E-12 F;Weak 25C = 8.13E-12 F
  • 2Ch = Nominal 25C = 7.69E-12 F;Strong 25C = 6.77E-12 F;Weak 25C = 8.29E-12 F
  • 2Dh = Nominal 25C = 7.83E-12 F;Strong 25C = 6.91E-12 F;Weak 25C = 8.44E-12 F
  • 2Eh = Nominal 25C = 7.97E-12 F;Strong 25C = 7.05E-12 F;Weak 25C = 8.60E-12 F
  • 2Fh = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 30h = Nominal 25C = 8.10E-12 F;Strong 25C = 7.18E-12 F;Weak 25C = 8.75E-12 F
  • 31h = Nominal 25C = 8.30E-12 F;Strong 25C = 7.38E-12 F;Weak 25C = 8.96E-12 F
  • 32h = Nominal 25C = 8.49E-12 F;Strong 25C = 7.57E-12 F;Weak 25C = 9.18E-12 F
  • 33h = Nominal 25C = 8.69E-12 F;Strong 25C = 7.76E-12 F;Weak 25C = 9.39E-12 F
  • 34h = Nominal 25C = 8.88E-12 F;Strong 25C = 7.94E-12 F;Weak 25C = 9.60E-12 F
  • 35h = Nominal 25C = 9.07E-12 F;Strong 25C = 8.13E-12 F;Weak 25C = 9.81E-12 F
  • 36h = Nominal 25C = 9.26E-12 F;Strong 25C = 8.32E-12 F;Weak 25C = 1.00E-11 F
  • 37h = Nominal 25C = 9.46E-12 F;Strong 25C = 8.51E-12 F;Weak 25C = 1.02E-11 F
  • 38h = Nominal 25C = 9.65E-12 F;Strong 25C = 8.70E-12 F;Weak 25C = 1.04E-11 F
  • 39h = Nominal 25C = 9.84E-12 F;Strong 25C = 8.89E-12 F;Weak 25C = 1.07E-11 F
  • 3Ah = Nominal 25C = 1.00E-11 F;Strong 25C = 9.07E-12 F;Weak 25C = 1.09E-11 F
  • 3Bh = Nominal 25C = 1.02E-11 F;Strong 25C = 9.26E-12 F;Weak 25C = 1.11E-11 F
  • 3Ch = Nominal 25C = 1.04E-11 F;Strong 25C = 9.45E-12 F;Weak 25C = 1.13E-11 F
  • 3Dh = Nominal 25C = 1.06E-11 F;Strong 25C = 9.64E-12 F;Weak 25C = 1.15E-11 F
  • 3Eh = Nominal 25C = 1.08E-11 F;Strong 25C = 9.82E-12 F;Weak 25C = 1.17E-11 F
  • 3Fh = Nominal 25C = 1.10E-11 F;Strong 25C = 1.00E-11 F;Weak 25C = 1.19E-11 F

6.6.8.40 AMPCFG0 Register (Offset = 124h) [Reset = 00000000h]

AMPCFG0 is shown in Table 6-146.

Return to the Summary Table.

Amplitude Compensation Configuration 0

Table 6-146 AMPCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-28Q2DLYR/W0hQ2CAP change delay.
Number of clock cycles to wait before changing Q2CAP by one step.
Clock frequency defined in FSMRATE.
27-24Q1DLYR/W0hQ1CAP change delay.
Number of clock cycles to wait before changing Q1CAP by one step.
Clock frequency defined in FSMRATE.
23-20ADCDLYR/W3hADC and PEAKDET startup time.
Number of clock cycles to wait after enabling the PEAKDET and ADC before the first measurement.
Clock frequency defined in FSMRATE.
19-15LDOSTARTR/W1FhLDO startup time.
Number of clock cycles to bypass the LDO resistors for faster startup.
Clock frequency defined in FSMRATE.
14-10INJWAITR/W2hInject HFOSC for faster HFXT startup.
This value specifies the number of clock cycles to wait after injection is done.
The clock speed is defined in FSMRATE.
9-5INJTIMER/W4hInject HFOSC for faster HFXT startup.
This value specifies the number of clock cycles the injection is enabled.
The clock speed is defined in FSMRATE.
Set to 0 to disable injection.
4-0FSMRATER/W2hUpdate rate for the AMPCOMP update rate.
Also affects the clock rate for the Amplitude ADC.
The update rate is 6MHz / (FSMRATE+1).
  • 0h = 6 MHz
  • 1h = 3 MHz
  • 2h = 2 MHz
  • 5h = 1 MHz
  • Bh = 500 kHz
  • 17h = 250 kHz

6.6.8.41 AMPCFG1 Register (Offset = 128h) [Reset = 00000000h]

AMPCFG1 is shown in Table 6-147.

Return to the Summary Table.

Amplitude Compensation Configuration 1

Table 6-147 AMPCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-28IDACDLYR/W2hIDAC change delay.
Time to wait before changing IDAC by one step.
This time needs to be long enough for the crystal to settle.
The number of clock cycles to wait is IDACDLY<<4 + 15.
Clock frequency defined in AMPCFG0.FSMRATE.
27-24IREFDLYR/W6hIREF change delay.
Number of clock cycles to wait before changing IREF by one step.
Clock frequency defined in AMPCFG0.FSMRATE.
23-12BIASLTR/WFFhLifetime of the amplitude ADC bias value.
This value specifies the number of adjustment intervals,
until the ADC bias value has to be measured again.
Set to 0 to disable automatic bias measurements.
11-0INTERVALR/WFFhInterval for amplitude adjustments.
Set to 0 to disable periodic adjustments.
This value specifies the number of clock cycles between adjustments.
The clock speed is defined in AMPCFG0.FSMRATE.

6.6.8.42 LOOPCFG Register (Offset = 12Ch) [Reset = 00000000h]

LOOPCFG is shown in Table 6-148.

Return to the Summary Table.

Configuration Register for the Tracking Loop

Table 6-148 LOOPCFG Register Field Descriptions
BitFieldTypeResetDescription
31-26FINETRIM_INITR/W18hInitial value for the resistor fine trim
25-21BOOST_TARGETR/W2hError-updates for 4xBOOST_TARGET times using KI_BOOST/KP_BOOST, before using KI/KP.
Note: If boost is used for long duration using large values of KI_BOOST and KP_BOOST, the oscillator frequency can reach well above the max frequence limit of the design, causing unexpected behaviour.
20-18KP_BOOSTR/W7hProportional loop coefficient during BOOST
17-15KI_BOOSTR/W4hIntegral loop coefficient during BOOST
14-10SETTLED_TARGETR/W13hNumber of HFOSC tracking loop updates before HFOSC is considered "settled". The tracking loop updates at a rough frequency of (2*Reference frequency/256).
If the reference frequency is 48MHz, the loop update frequency comes out to be 375Khz.
Internally the MMR is multiplied by 4
9-6OOR_LIMITR/WEhOut-of-range threshold. OOR_LIMIT is compared with absolute value of 5 MSB bits of loop filter error.
5-3KPR/W6hProportional loop coefficient
2-0KIR/W2hIntegral loop coefficient

6.6.8.43 LOOPCFG1 Register (Offset = 130h) [Reset = 00000000h]

LOOPCFG1 is shown in Table 6-149.

Return to the Summary Table.

Configuration Register for underclocking HFOSC

Table 6-149 LOOPCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25SETTLEIRQR/W0hConfiguration to enable the interrupt when the HFOSC tracking loop has settled. The interrupt will be based on LOOPCFG.SETTLED_TARGET.
  • 0h = Disable the interrupt to indicate that HFOSC tracking loop has settled.
  • 1h = Enable the interrupt to indicate that HFOSC tracking loop has settled.
24-6UNDERCLKCNTR/WXhTimer to trigger HFOSC underclocking. The timer will run at approximately 32.768 KHz.
5-0KIOFFR/W3FhBased on HFTRACKCTRL.UNDERCLK configuration, after an event is triggerred, KI of the HFOSC tracking loop will be reduced by this amount.

6.6.8.44 AFOSCCTL Register (Offset = 140h) [Reset = 00000000h]

AFOSCCTL is shown in Table 6-150.

Return to the Summary Table.

Audio frequency oscillator control

Table 6-150 AFOSCCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24PWW0hPassword protection for QUALBYP.
Write this field to 0xA5 to accept writes to QUALBYP.
23-3RESERVEDR0hReserved
2AUTODISR/W0hIf set, AFOSC can be disabled by PMCTL upon standby entry. EN bit will be overriden with a value 0 and user has to manually re-enable AFOSC.
1QUALBYPR/W0hClock qualification bypass.
AFOSC qualification will skip a fixed number of clock cycles to prevent glitches
or frequency overshoots from reaching the system. Setting this bit will bypass the qualification.
This bit can be locked in SYS0. If unlocked, it is password protected with PW.
0ENR/W0hEnable AFOSC.

6.6.8.45 AFTRACKCTL Register (Offset = 144h) [Reset = 00000000h]

AFTRACKCTL is shown in Table 6-151.

Return to the Summary Table.

Audio frequency tracking loop control

Table 6-151 AFTRACKCTL Register Field Descriptions
BitFieldTypeResetDescription
31ENR/W0hEnable tracking loop.
30DSMBYPR/W0hBypass Delta-Sigma-Modulation of fine trim.
29-0RATIOR/W0999999AhRatio. Ratio format is 0b.30b
  • 07D6343Fh = 131478591
  • 088190ACh = 142708908
  • 08EE23B9h = 149824441
  • 0999999Ah = 161061274
  • 09B8B578h = 163100024

6.6.8.46 BANDGAPCTL Register (Offset = 148h) [Reset = 00000000h]

BANDGAPCTL is shown in Table 6-152.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 6-152 BANDGAPCTL Register Field Descriptions
BitFieldTypeResetDescription
31BGOVRR/W0hInternal. Only to be used through TI provided API.
30-4RESERVEDR0hReserved
3VBGAPBYPR/W0hInternal. Only to be used through TI provided API.
2VBGAPREFENR/W0hInternal. Only to be used through TI provided API.
1VDDRREFENR/W0hInternal. Only to be used through TI provided API.
0REFENR/W0hInternal. Only to be used through TI provided API.

6.6.8.47 AFCLKSEL Register (Offset = 150h) [Reset = 00000000h]

AFCLKSEL is shown in Table 6-153.

Return to the Summary Table.

Audio clock selection

Table 6-153 AFCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0SRCR/W0hSelect audio frequency clock source
Software should make sure that proper clock is selected before enabling the audio IP.
  • 0h = Clock disabled
  • 1h = AFOSC clock
  • 2h = 96MHz CLKHF
  • 3h = 48MHz reference clock (HFXT)
  • 4h = External clock

6.6.8.48 CANCLKSEL Register (Offset = 154h) [Reset = 00000000h]

CANCLKSEL is shown in Table 6-154.

Return to the Summary Table.

CAN clock selection

Table 6-154 CANCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SRCR/W0hSelect audio frequency clock source
Software should make sure that proper clock is selected before enabling the audio IP.
  • 0h = Clock disabled
  • 1h = AFOSC clock
  • 2h = 96MHz CLKHF

6.6.8.49 TRACKSTATAF Register (Offset = 160h) [Reset = 00000000h]

TRACKSTATAF is shown in Table 6-155.

Return to the Summary Table.

AF tracking loop status information

Table 6-155 TRACKSTATAF Register Field Descriptions
BitFieldTypeResetDescription
31LOOPERRVLDR0hCurrent AFOSC tracking error valid
This bit is one if the tracking loop is running and the error value is valid.
30RESERVEDR0hReserved
29-16LOOPERRR0hCurrent AFOSC tracking error
This field uses the internal fractional representation (sign, 9 integer bits, 4 fractional bits).
The actual fine trim value of format (sign, 9 integer bits, 30 fractional bits) is saturated to (sign, 9 integer bits, 4 fractional bits).
15-13RESERVEDR0hReserved
12-0FINETRIMR1D80hCurrent AFOSC Fine-trim value
This field uses the internal fractional representation (sign, 5 integer bits, 7 fractional bits).
The actual fine trim value of format (sign, 5 integer bits, 19 fractional bits) is saturated to (sign, 5 integer bits, 7 fractional bits).
The actual trim value applied to the oscillator is delta-sigma modulated 6 bits non-signed
(inverted sign bit + integer bits).

6.6.8.50 TRACKSTATAF1 Register (Offset = 164h) [Reset = 00000000h]

TRACKSTATAF1 is shown in Table 6-156.

Return to the Summary Table.

AF tracking loop status information

Table 6-156 TRACKSTATAF1 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-0LOOPERRR0hCurrent AFOSC tracking error
This field uses the fractional representation of the actual error(30 fractional bits). The actual error is of format (sign, 9 integer bits, 30 fractional bits).

6.6.8.51 TRACKSTATAF2 Register (Offset = 168h) [Reset = 00000000h]

TRACKSTATAF2 is shown in Table 6-157.

Return to the Summary Table.

AF tracking loop status information

Table 6-157 TRACKSTATAF2 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24-0FINETRIMR01D80000hCurrent AFOSC Fine-trim value
This field uses the internal fractional representation (sign, 5 integer bits, 19 fractional bits).
The actual trim value applied to the oscillator is delta-sigma modulated 6 bits non-signed
(inverted sign bit + integer bits).

6.6.8.52 LOOPCFGAF Register (Offset = 170h) [Reset = 00000000h]

LOOPCFGAF is shown in Table 6-158.

Return to the Summary Table.

Configuration Register for the Audio frequency Tracking Loop

Table 6-158 LOOPCFGAF Register Field Descriptions
BitFieldTypeResetDescription
31-26FINETRIM_INITR/WChInitial value for the resistor fine trim
25-21BOOST_TARGETR/W2hNumber of error-updates using BOOST values, before using KI/KP
20-18KP_BOOSTR/W7hProportional loop coefficient during BOOST
17-15KI_BOOSTR/W4hIntegral loop coefficient during BOOST
14-10SETTLED_TARGETR/WChNumber of updates before AFOSC is considered "settled"
9-6OOR_LIMITR/WEhOut-of-range threshold. Out-of-range threshold. OOR_LIMIT is compared with absolute value of 5 MSB bits of loop filter error.
5-3KPR/W6hProportional loop coefficient
2-0KIR/W3hIntegral loop coefficient

6.6.8.53 CTL Register (Offset = 200h) [Reset = 00000000h]

CTL is shown in Table 6-159.

Return to the Summary Table.

Control

Table 6-159 CTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0CMDW0hTDC commands.
  • 0h = Clear [TDC.STAT.SAT], [TDC.STAT.DONE], and [TDC.RESULT.VALUE]. ;This is not needed as prerequisite for a measurement. Reliable clear is only guaranteed from IDLE state.
  • 1h = Synchronous counter start.;The counter looks for the opposite edge of the selected start event before it starts to count when the selected edge occurs. This guarantees an edge-triggered start and is recommended for frequency measurements.
  • 2h = Asynchronous counter start.;The counter starts to count when the start event is high. To achieve precise edge-to-edge measurements you must ensure that the start event is low for at least 420 ns after you write this command.
  • 3h = Force TDC state machine back to IDLE state.;Never write this command while [TDC.STAT.STATE] equals CLR_CNT or WAIT_CLR_CNT_DONE.

6.6.8.54 STAT Register (Offset = 204h) [Reset = 00000000h]

STAT is shown in Table 6-160.

Return to the Summary Table.

Status

Table 6-160 STAT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7SATR0hTDC measurement saturation flag.
0: Conversion has not saturated.
1: Conversion stopped due to saturation.
This field is cleared when a new measurement is started or when CLR_RESULT is written to [TDC.CTL.CMD].
6DONER0hTDC measurement complete flag.
0: TDC measurement has not yet completed.
1: TDC measurement has completed.
This field clears when a new TDC measurement starts or when you write CLR_RESULT to [TDC.CTL.CMD].
5-0STATER6hTDC state machine status.
  • 0h = Current state is TDC_STATE_WAIT_START. ;The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment.
  • 4h = Current state is TDC_STATE_WAIT_STARTSTOPCNTEN.;The fast-counter circuit looks for the start condition. The state machine waits for the fast-counter to increment.
  • 6h = Current state is TDC_STATE_IDLE. ;This is the default state after reset and abortion. State will change when you write [TDC.CTL.CMD] to either RUN_SYNC_START or RUN.
  • 7h = Current state is TDC_STATE_CLRCNT. The fast-counter circuit is reset.
  • 8h = Current state is TDC_STATE_WAIT_STOP.;The state machine waits for the fast-counter circuit to stop.
  • Ch = Current state is TDC_STATE_WAIT_STOPCNTDOWN.;The fast-counter circuit looks for the stop condition. It will ignore a number of stop events configured in [TDC.TRIGCNTLOAD.CNT].
  • Eh = Current state is TDC_STATE_GETRESULTS.;The state machine copies the counter value from the fast-counter circuit.
  • Fh = Current state is TDC_STATE_POR. ;This is the reset state.
  • 16h = Current state is TDC_STATE_WAIT_CLRCNT_DONE. ;The state machine waits for fast-counter circuit to finish reset.
  • 1Eh = Current state is TDC_WAIT_STARTFALL. ;The fast-counter circuit waits for a falling edge on the start event.
  • 2Eh = Current state is TDC_FORCESTOP.;You wrote ABORT to [TDC.CTL.CMD] to abort the TDC measurement.

6.6.8.55 RESULT Register (Offset = 208h) [Reset = 00000000h]

RESULT is shown in Table 6-161.

Return to the Summary Table.

Result
Result of last TDC conversion.

Table 6-161 RESULT Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER2hTDC conversion result.
The result of the TDC conversion is given in number of clock edges of the clock source selected in [IPSPECIFIC.CKM.TDCCLKSEL.REFCLK]. Both rising and falling edges are counted.
Note that [TDC.SATCFG.LIMIT] is given in periods, while VALUE is given in edges (periods*2).
If TDC counter saturates, VALUE is slightly higher than [TDC.SATCFG.LIMIT]*2, as it takes a non-zero time to stop the measurement. Hence, the maximum value of this field becomes slightly higher than 231 (230 periods*2) if you configure [TDC.SATCFG.LIMIT] to R30.

6.6.8.56 SATCFG Register (Offset = 20Ch) [Reset = 00000000h]

SATCFG is shown in Table 6-162.

Return to the Summary Table.

Saturation Configuration

Table 6-162 SATCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-0LIMITR/W0hSaturation limit.
The flag [TDC.STAT.SAT] is set when the TDC counter saturates.
Note that this value is given in periods, while [TDC.RESULT.VALUE] is given in edges (periods*2).
Values not enumerated are not supported
  • 0h = No saturation. An additional timer should be used to know if [TDC.RESULT.VALUE] rolled over.
  • 3h = TDC conversion saturates and stops after 212 periods.
  • 4h = TDC conversion saturates and stops after 213 periods.
  • 5h = TDC conversion saturates and stops after 214 periods.
  • 6h = TDC conversion saturates and stops after 215 periods.
  • 7h = TDC conversion saturates and stops after 216 periods.
  • 8h = TDC conversion saturates and stops after 217 periods.
  • 9h = TDC conversion saturates and stops after 218 periods.
  • Ah = TDC conversion saturates and stops after 219 periods.
  • Bh = TDC conversion saturates and stops after 220 periods.
  • Ch = TDC conversion saturates and stops after 221 periods.
  • Dh = TDC conversion saturates and stops after 222 periods.
  • Eh = TDC conversion saturates and stops after 223 periods.
  • Fh = TDC conversion saturates and stops after 224 periods.
  • 10h = TDC conversion saturates and stops after 225 periods.
  • 11h = TDC conversion saturates and stops after 226 periods.
  • 12h = TDC conversion saturates and stops after 227 periods.
  • 13h = TDC conversion saturates and stops after 228 periods.
  • 14h = TDC conversion saturates and stops after 229 periods.
  • 15h = TDC conversion saturates and stops after 230 periods.

6.6.8.57 TRIGSRC Register (Offset = 210h) [Reset = 00000000h]

TRIGSRC is shown in Table 6-163.

Return to the Summary Table.

Trigger Source
Select source and polarity for TDC start and stop events. See the Technical Reference Manual for event timing requirements.

Table 6-163 TRIGSRC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15STOP_POLR/W0hPolarity of stop source.
Change only while [TDC.STAT.STATE] is IDLE.
  • 0h = TDC conversion stops when high level is detected.
  • 1h = TDC conversion stops when low level is detected.
14-13RESERVEDR0hReserved
12-8STOP_SRCR/W0hSelect stop source from the asynchronous AUX event bus.
Change only while [TDC.STAT.STATE] is IDLE.
  • 0h = LFTICK signal going to the RTC
  • 1h = Low frequency on-chip oscillator
  • 2h = Low frequency crystal oscillator
  • 3h = Delayed version of selected LFCLK
  • 4h = General purpose input signal
  • 5h = Digital testbus bit 0
  • 6h = Digital testbus bit 1
  • 7h = Digital testbus bit 2
  • 8h = Digital testbus bit 3
  • 9h = Digital testbus bit 4
  • Ah = Digital testbus bit 5
  • Bh = Digital testbus bit 6
  • Ch = Digital testbus bit 7
  • Dh = Digital testbus bit 8
  • Eh = Digital testbus bit 9
  • Fh = Digital testbus bit 10
  • 10h = Digital testbus bit 11
  • 11h = Digital testbus bit 12
  • 12h = Digital testbus bit 13
  • 13h = Digital testbus bit 14
  • 14h = Digital testbus bit 15
  • 1Fh = Select TDC Prescaler event which is generated by configuration of TDC.PRECTL.
7START_POLR/W0hPolarity of start source.
Change only while [TDC.STAT.STATE] is IDLE.
  • 0h = TDC conversion starts when high level is detected.
  • 1h = TDC conversion starts when low level is detected.
6-5RESERVEDR0hReserved
4-0START_SRCR/W0hSelect start source from the asynchronous AUX event bus.
Change only while [TDC.STAT.STATE] is IDLE.
  • 0h = LFTICK signal going to the RTC
  • 1h = Low frequency on-chip oscillator
  • 2h = Low frequency crystal oscillator
  • 3h = Delayed version of selected LFCLK
  • 4h = General purpose input signal
  • 5h = Digital testbus bit 0
  • 6h = Digital testbus bit 1
  • 7h = Digital testbus bit 2
  • 8h = Digital testbus bit 3
  • 9h = Digital testbus bit 4
  • Ah = Digital testbus bit 5
  • Bh = Digital testbus bit 6
  • Ch = Digital testbus bit 7
  • Dh = Digital testbus bit 8
  • Eh = Digital testbus bit 9
  • Fh = Digital testbus bit 10
  • 10h = Digital testbus bit 11
  • 11h = Digital testbus bit 12
  • 12h = Digital testbus bit 13
  • 13h = Digital testbus bit 14
  • 14h = Digital testbus bit 15
  • 1Fh = Select TDC Prescaler event which is generated by configuration of TDC.PRECTL.

6.6.8.58 TRIGCNT Register (Offset = 214h) [Reset = 00000000h]

TRIGCNT is shown in Table 6-164.

Return to the Summary Table.

Trigger Counter
Stop-counter control and status.

Table 6-164 TRIGCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CNTR/W0hNumber of stop events to ignore when [TDC.TRIGCNTCFG.EN] is 1.
Read CNT to get the remaining number of stop events to ignore during a TDC measurement.
Write CNT to update the remaining number of stop events to ignore during a TDC measurement. The TDC measurement ignores updates of CNT if there are no more stop events left to ignore.
When [TDC.TRIGCNTCFG.EN] is 1, [TDC.TRIGCNTLOAD.CNT] is loaded into CNT at the start of the measurement.

6.6.8.59 TRIGCNTLOAD Register (Offset = 218h) [Reset = 00000000h]

TRIGCNTLOAD is shown in Table 6-165.

Return to the Summary Table.

Trigger Counter Load
Stop-counter load.

Table 6-165 TRIGCNTLOAD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CNTR/W0hNumber of stop events to ignore when [TDC.TRIGCNTCFG.EN] is 1.
To measure frequency of an event source:
- Set start event equal to stop event.
- Set CNT to number of periods to measure. Both 0 and 1 values measures a single event source period.
To measure pulse width of an event source:
- Set start event source equal to stop event source.
- Select different polarity for start and stop event.
- Set CNT to 0.
To measure time from the start event to the Nth stop event when N > 1:
- Select different start and stop event source.
- Set CNT to (N-1).
See the Technical Reference Manual for event timing requirements.
When [TDC.TRIGCNTCFG.EN] is 1, CNT is loaded into [TDC.TRIGCNT.CNT] at the start of the measurement.

6.6.8.60 TRIGCNTCFG Register (Offset = 21Ch) [Reset = 00000000h]

TRIGCNTCFG is shown in Table 6-166.

Return to the Summary Table.

Trigger Counter Configuration
Stop-counter configuration.

Table 6-166 TRIGCNTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hEnable stop-counter.
0: Disable stop-counter.
1: Enable stop-counter.
Change only while [TDC.STAT.STATE] is IDLE.

6.6.8.61 PRECTL Register (Offset = 220h) [Reset = 00000000h]

PRECTL is shown in Table 6-167.

Return to the Summary Table.

Prescaler Control
The prescaler can be used to count events that are faster than the bus rate.
It can be used to:
- count pulses on a specified event from the asynchronous event bus.
- prescale a specified event from the asynchronous event bus.
To use the prescaler output as an event source in TDC measurements you must set both TRIGSRC.START_SRC and TRIGSRC.STOP_SRC to TDC_PRE.
It is recommended to use the prescaler when the signal frequency to measure exceeds 1/10th of the bus rate.

Table 6-167 PRECTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RESET_NR/W0hPrescaler reset.
0: Reset prescaler.
1: Release reset of prescaler.
AUX_TDC_PRE event becomes 0 when you reset the prescaler.
6RATIOR/W0hPrescaler ratio.
This controls how often the TDC_PRE event is generated by the prescaler.
  • 0h = Prescaler divides input by 16. ;AUX_TDC_PRE event has a rising edge for every 16 rising edges of the input. AUX_TDC_PRE event toggles on every 8th rising edge of the input.
  • 1h = Prescaler divides input by 64. ;AUX_TDC_PRE event has a rising edge for every 64 rising edges of the input. AUX_TDC_PRE event toggles on every 32nd rising edge of the input.
5RESERVEDR0hReserved
4-0SRCR/W0hPrescaler event source.
Select an event from the asynchronous AUX event bus to connect to the prescaler input.
Configure only while RESET_N is 0.
  • 0h = LFTICK signal going to the RTC
  • 1h = Low frequency on-chip oscillator
  • 2h = Low frequency crystal oscillator
  • 3h = Delayed version of selected LFCLK
  • 4h = General purpose input signal
  • 5h = Digital testbus bit 0
  • 6h = Digital testbus bit 1
  • 7h = Digital testbus bit 2
  • 8h = Digital testbus bit 3
  • 9h = Digital testbus bit 4
  • Ah = Digital testbus bit 5
  • Bh = Digital testbus bit 6
  • Ch = Digital testbus bit 7
  • Dh = Digital testbus bit 8
  • Eh = Digital testbus bit 9
  • Fh = Digital testbus bit 10
  • 10h = Digital testbus bit 11
  • 11h = Digital testbus bit 12
  • 12h = Digital testbus bit 13
  • 13h = Digital testbus bit 14
  • 14h = Digital testbus bit 15
  • 15h = High frequency on-chip oscillator
  • 16h = High frequency crystal oscillator
  • 17h = Audio frequency on-chip oscillator

6.6.8.62 PRECNTR Register (Offset = 224h) [Reset = 00000000h]

PRECNTR is shown in Table 6-168.

Return to the Summary Table.

Prescaler Counter

Table 6-168 PRECNTR Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16CAPTW0hPrescaler counter capture strobe.
Write a 1 to CAPT to capture the value of the 16-bit prescaler counter into CNT. Read CNT to get the captured value.
15-0CNTR0hPrescaler counter value.
Write a 1 to CAPT to capture the value of the 16-bit prescaler counter into CNT. Read CNT to get the captured value.
The read value gets 1 LSB uncertainty if the event source level rises when you release the reset.
The read value gets 1 LSB uncertainty if the event source level rises when you capture the prescaler counter.
Please note the following:
- The prescaler counter is reset to 3 by [TDC.PRECTL.RESET_N].
- The captured value is 3 when the number of rising edges on prescaler input is less than 3. Otherwise, captured value equals number of event pulses.

6.6.8.63 CNT Register (Offset = 300h) [Reset = 00000000h]

CNT is shown in Table 6-169.

Return to the Summary Table.

WDT counter value register

Table 6-169 CNT Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCounter value.
A write to this field immediately starts (or restarts) the counter. It will count down from the written value.
If the counter reaches 0, a reset will be generated.
A write value of 0 immediately generates a reset.
This field is only writable if not locked. See LOCK register.
Writing this field will automatically activate the lock.
A read returns the current value of the counter.

6.6.8.64 TEST Register (Offset = 304h) [Reset = 00000000h]

TEST is shown in Table 6-170.

Return to the Summary Table.

WDT test mode register

Table 6-170 TEST Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STALLENR/W0hWDT stall enable
This field is only writable if not locked. See LOCK register.
  • 0h = DISABLE;WDT continues counting while the CPU is stopped by a debugger.
  • 1h = ENABLE;WDT stops counting while the CPU is stopped by a debugger.

6.6.8.65 LOCK Register (Offset = 308h) [Reset = 00000000h]

LOCK is shown in Table 6-171.

Return to the Summary Table.

WDT lock register

Table 6-171 LOCK Register Field Descriptions
BitFieldTypeResetDescription
31-0STATR/W1hA write with value 0x1ACCE551 unlocks the watchdog registers for write access.
A write with any other value locks the watchdog registers for write access.
Writing the CNT register will also lock the watchdog registers.
A read of this field returns the state of the lock (0=unlocked, 1=locked).