SWCU195A December   2024  – May 2025 CC2744R7-Q1 , CC2745P10-Q1 , CC2745R10-Q1 , CC2745R7-Q1 , CC2755P10 , CC2755R10

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M33
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
      5. 1.3.5 TI Machine Learning Instruction Extensions
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDIO
      3. 1.5.3 VDDR
      4. 1.5.4 VDDD Digital Core Supply
      5. 1.5.5 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  Hardware Security Module
    8. 1.8  AES 128-Bit Cryptographic Accelerator
    9. 1.9  System Timer (SYSTIM)
    10. 1.10 General Purpose Timers (LGPT)
    11. 1.11 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.11.1 Watchdog Timer
      2. 1.11.2 Battery and Temperature Monitor
      3. 1.11.3 Voltage Glitch Monitor (VGM)
      4. 1.11.4 Real-Time Clock (RTC)
      5. 1.11.5 Low Power Comparator
    12. 1.12 Direct Memory Access
    13. 1.13 System Control and Clock
    14. 1.14 Communication Peripherals
      1. 1.14.1 UART
      2. 1.14.2 I2C
      3. 1.14.3 SPI
      4. 1.14.4 CAN-FD
      5. 1.14.5 I2S
    15. 1.15 Programmable I/Os
    16. 1.16 Algorithm Processing Unit (APU)
    17. 1.17 Serial Wire Debug (SWD)
  4. 2 Arm® Cortex®-M33 Processor
    1. 2.1 Arm® Cortex®-M33 Processor Introduction
    2. 2.2 M33 Instantiation Parameters
    3. 2.3 Arm® Cortex®-M33 System Peripheral Details
      1. 2.3.1 Floating Point Unit (FPU)
      2. 2.3.2 Memory Protection Unit (MPU)
      3. 2.3.3 Digital Signal Processing (DSP)
      4. 2.3.4 Security Attribution Unit (SAU)
      5. 2.3.5 System Timer (SysTick)
      6. 2.3.6 Nested Vectored Interrupt Controller (NVIC)
      7. 2.3.7 System Control Block (SCB)
      8. 2.3.8 System Control Space (SCS)
    4. 2.4 CPU Sub-System Peripheral Details
      1. 2.4.1 Trace Port Interface Unit (TPIU)
      2. 2.4.2 DAP Bridge and Debug Authentication
      3. 2.4.3 Implementation Defined Attribution Unit (IDAU)
      4. 2.4.4 Custom Datapath Extension (CDE)
    5. 2.5 Programming Model
      1. 2.5.1 Modes of Operation and Execution
        1. 2.5.1.1 Security States
        2. 2.5.1.2 Operating Modes
        3. 2.5.1.3 Operating States
        4. 2.5.1.4 Privileged Access and Unprivileged User Access
      2. 2.5.2 Instruction Set Summary
      3. 2.5.3 Memory Model
        1. 2.5.3.1 Private Peripheral Bus
        2. 2.5.3.2 Unaligned Accesses
      4. 2.5.4 Processor Core Registers Summary
      5. 2.5.5 Exceptions
        1. 2.5.5.1 Exception Handling and Prioritization
    6. 2.6 TrustZone-M
      1. 2.6.1 Overview
      2. 2.6.2 M33 Configuration
      3. 2.6.3 Description of Elements
        1. 2.6.3.1 IDAU (Implementation Defined Attribution Unit)
          1. 2.6.3.1.1 Expected Use
        2. 2.6.3.2 Gaskets
          1. 2.6.3.2.1 Periphery Gasket
          2. 2.6.3.2.2 Controller Gasket
        3. 2.6.3.3 Memories
        4. 2.6.3.4 TCM
      4. 2.6.4 TCM Registers
    7. 2.7 Arm® Cortex®-M33 Registers
      1. 2.7.1  CPU_ROM_TABLE Registers
      2. 2.7.2  TPIU Registers
      3. 2.7.3  DCB Registers
      4. 2.7.4  DIB Registers
      5. 2.7.5  DWT Registers
      6. 2.7.6  FPB Registers
      7. 2.7.7  FPE Registers
      8. 2.7.8  ICB Registers
      9. 2.7.9  ITM Registers
      10. 2.7.10 MPU Registers
      11. 2.7.11 NVIC Registers
      12. 2.7.12 SAU Registers
      13. 2.7.13 SCB Registers
      14. 2.7.14 SYSTIMER Registers
      15. 2.7.15 SYSTICK Registers
      16. 2.7.16 Clock Control
      17. 2.7.17 Protocol Descriptions
      18. 2.7.18 Reset Considerations
        1. 2.7.18.1 Hardware Reset Considerations
      19. 2.7.19 Initialization
      20. 2.7.20 Interrupt and Event Support
        1. 2.7.20.1 Connection to Event Fabric
      21. 2.7.21 Power Management
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Interrupt Priority Grouping
      7. 4.1.7 Exception Entry and Return
        1. 4.1.7.1 Exception Entry
        2. 4.1.7.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Fault Types
      2. 4.2.2 Fault Escalation to HardFault
      3. 4.2.3 Fault Status Registers and Fault Address Registers
      4. 4.2.4 Lockup
    3. 4.3 Security State Switches
    4. 4.4 Event Fabric
      1. 4.4.1 Introduction
      2. 4.4.2 Overview
      3. 4.4.3 Registers
      4. 4.4.4 AON Event Fabric
        1. 4.4.4.1 AON Common Input Events List
        2. 4.4.4.2 AON Event Subscribers
        3. 4.4.4.3 Power Management Controller (PMCTL)
        4. 4.4.4.4 Real Time Clock (RTC)
        5. 4.4.4.5 AON to MCU Event Fabric
      5. 4.4.5 MCU Event Fabric
        1. 4.4.5.1 Common Input Event List
        2. 4.4.5.2 MCU Event Subscribers
          1. 4.4.5.2.1 System CPU
          2. 4.4.5.2.2 Non-Maskable Interrupt (NMI)
    5. 4.5 Digital Test Bus (DTB)
    6. 4.6 EVTSVT Registers
    7. 4.7 EVTULL Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1 Introduction
    2. 6.2 System CPU Modes
    3. 6.3 Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4 Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
      6. 6.4.6 PMCTL Registers
    5. 6.5 Digital Power Partitioning
    6. 6.6 Clocks
      1. 6.6.1 Block Diagram
      2. 6.6.2 LF clock
        1. 6.6.2.1 LFINC Measurement Mechanism
        2. 6.6.2.2 LFINC Filtering
      3. 6.6.3 HFOSC
        1. 6.6.3.1 HFOSC Control and Qualification
        2. 6.6.3.2 HFOSC Tracking Loop
      4. 6.6.4 AFOSC
        1. 6.6.4.1 AFOSC Control and Qualification
        2. 6.6.4.2 AFOSC Tracking Loop
        3. 6.6.4.3 AFOSC Ratio
      5. 6.6.5 CLKSVT
      6. 6.6.6 CLKULL
      7. 6.6.7 CKM Registers
      8. 6.6.8 CKMD Registers
      9. 6.6.9 CLKCTL Registers
    7. 6.7 Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 RTC Reset
      3. 6.7.3 LF Loss Detection
    8. 6.8 AON (REG3V3) Register Bank
  9. 7 Internal Memory
    1. 7.1 SRAM
      1. 7.1.1 Overview
        1. 7.1.1.1 Purpose of the Peripheral
        2. 7.1.1.2 Features
        3. 7.1.1.3 Functional Block Diagram
      2. 7.1.2 Peripheral Functional Description
        1. 7.1.2.1 Parity Error Detection
          1. 7.1.2.1.1 Parity Error Debug Register
        2. 7.1.2.2 Extension Mode
        3. 7.1.2.3 Initialization
        4. 7.1.2.4 TrustZone Watermarking
      3. 7.1.3 SRAM Registers
      4. 7.1.4 SRAMCTRL Registers
    2. 7.2 VIMS
      1. 7.2.1 Overview
        1. 7.2.1.1 Purpose of the Peripheral
        2. 7.2.1.2 Features
        3. 7.2.1.3 Functional Block Diagram
      2. 7.2.2 Peripheral Functional Description
        1. 7.2.2.1 Dedicated 8KB CPU Cache
        2. 7.2.2.2 Dedicated 2KB HSM Cache
        3. 7.2.2.3 Dedicated 128-Bit Line Buffer
        4. 7.2.2.4 ROM
        5. 7.2.2.5 Flash
        6. 7.2.2.6 Auxiliary Regions
        7. 7.2.2.7 Flash Partition and Protection
          1. 7.2.2.7.1 Main Region
          2. 7.2.2.7.2 Read Protection
          3. 7.2.2.7.3 Sticky Write/Erase Protection
        8. 7.2.2.8 TrustZoneTM Watermark
        9. 7.2.2.9 Debug Access
      3. 7.2.3 VIMS Registers
    3. 7.3 FLASH
      1. 7.3.1 FLASH Registers
  10. 8 Hardware Security Module (HSM)
    1. 8.1 Introduction
    2. 8.2 Overview
    3. 8.3 One-Time-Programmable (OTP) Controller
      1. 8.3.1 High-Level Sequence to Handle OTP Requests
    4. 8.4 Mailbox and Register Access Firewall
    5. 8.5 DMA Firewall
    6. 8.6 Coprocessor
    7. 8.7 HSM FW
      1. 8.7.1 Acquiring the Latest HSM FW
      2. 8.7.2 Programming HSM FW
      3. 8.7.3 Optional Customer Signing of HSM FW
    8. 8.8 HSM Registers
    9. 8.9 HSMCRYPTO Registers
  11. 9 Device Boot and Bootloader
    1. 9.1 Device Boot and Programming
      1. 9.1.1 Boot Flow
      2. 9.1.2 Boot Status
      3. 9.1.3 Boot Protection/Locking Mechanisms
      4. 9.1.4 Debug and Active SWD Connections at Boot
        1. 9.1.4.1 Secure Debug and Persistent Debug
      5. 9.1.5 Flashless Test Mode and Tools Client Mode
        1. 9.1.5.1 Flashless Test Mode
        2. 9.1.5.2 Tools Client Mode
      6. 9.1.6 Retest Mode and Return-to-Factory Procedure
      7. 9.1.7 Disabling SWD Debug Port
    2. 9.2 Flash Programming
      1. 9.2.1 CCFG
      2. 9.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 9.2.3 SACI Flash Programming Commands
      4. 9.2.4 Flash Programming Flows
        1. 9.2.4.1 Initial Programming of a New Device
        2. 9.2.4.2 Reprogramming of Previously Programmed Device
        3. 9.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 9.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 9.2.4.5 Reprogramming of Only the Main Flash Application of a Previously Programmed Device
    3. 9.3 Device Management Command Interface
      1. 9.3.1 SACI Communication Protocol
        1. 9.3.1.1 Host Side Protocol
        2. 9.3.1.2 Command Format
        3. 9.3.1.3 Response Format
        4. 9.3.1.4 Response Result Field
        5. 9.3.1.5 Command Sequence Tag
        6. 9.3.1.6 Host Side Timeout
      2. 9.3.2 SACI Commands
        1. 9.3.2.1 Miscellaneous Commands
          1. 9.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 9.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 9.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
          4. 9.3.2.1.4 SACI_CMD_GET_SECBOOT_HSMFW_UPDATE_STATUS
          5. 9.3.2.1.5 SACI_CMD_HSM_GET_SYS_INFO
        2. 9.3.2.2 Debug Commands
          1. 9.3.2.2.1 SACI_CMD_DEBUG_EXIT_SACI_HALT
          2. 9.3.2.2.2 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          3. 9.3.2.2.3 SACI_CMD_DEBUG_REQ_KEY_ID
          4. 9.3.2.2.4 SACI_CMD_DEBUG_REQ_CHALLENGE
          5. 9.3.2.2.5 SACI_CMD_DEBUG_SUBMIT_CHALLENGE_RESP
          6. 9.3.2.2.6 SACI_CMD_DEBUG_CLOSE_SESSION
          7. 9.3.2.2.7 SACI_CMD_BLDR_APP_RESET_DEVICE
          8. 9.3.2.2.8 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 9.3.2.3 Flash Programming Commands
          1. 9.3.2.3.1  SACI_CMD_FLASH_ERASE_CHIP
          2. 9.3.2.3.2  SACI_CMD_FLASH_ERASE_MAIN_APP
          3. 9.3.2.3.3  SACI_CMD_FLASH_PROG_CCFG_SECTOR
          4. 9.3.2.3.4  SACI_CMD_FLASH_PROG_CCFG_USER_REC
          5. 9.3.2.3.5  SACI_CMD_FLASH_PROG_SCFG_SECTOR
          6. 9.3.2.3.6  SACI_CMD_FLASH_PROG_MAIN_SECTOR
          7. 9.3.2.3.7  SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          8. 9.3.2.3.8  SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          9. 9.3.2.3.9  SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
          10. 9.3.2.3.10 SACI_CMD_FLASH_VERIFY_SCFG_SECTOR
    4. 9.4 Bootloader Support
      1. 9.4.1 Bootloader v.s Secure Boot
    5. 9.5 ROM Serial Bootloader
      1. 9.5.1 ROM Serial Bootloader Interfaces
        1. 9.5.1.1 Packet Handling
          1. 9.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 9.5.1.2 Transport Layer
          1. 9.5.1.2.1 UART Transport
            1. 9.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 9.5.1.2.2 SPI Transport
      2. 9.5.2 ROM Serial Bootloader Parameters
      3. 9.5.3 ROM Serial Bootloader Commands
        1. 9.5.3.1 BLDR_CMD_PING
        2. 9.5.3.2 BLDR_CMD_GET_STATUS
        3. 9.5.3.3 BLDR_CMD_GET_PART_ID
        4. 9.5.3.4 BLDR_CMD_RESET
        5. 9.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 9.5.3.6 BLDR_CMD_CRC32
        7. 9.5.3.7 BLDR_CMD_DOWNLOAD
        8. 9.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 9.5.3.9 BLDR_CMD_SEND_DATA
      4. 9.5.4 Bootloader Firmware Update Example
  12. 10Device Configuration
    1. 10.1 Guidelines for Securely Configuring Your Device
      1. 10.1.1 Enabling and Configuring Secure Boot
      2. 10.1.2 Configure Debug Access
      3. 10.1.3 Configure Flash Protections
      4. 10.1.4 Configure Device Permissions
      5. 10.1.5 Configure HSM FW Update Keys
      6. 10.1.6 Configure emSensor
    2. 10.2 Factory Configuration (FCFG)
    3. 10.3 Customer Configuration (CCFG)
    4. 10.4 Security Configuration (SCFG)
  13. 11Secure Boot
    1. 11.1  Secure Boot
    2. 11.2  Execution Flow
    3. 11.3  ROM API
      1. 11.3.1 HAPI (Hardware API)
      2. 11.3.2 Registers
    4. 11.4  Configuration
      1. 11.4.1 Slot Configuration
      2. 11.4.2 Policy
        1. 11.4.2.1 Authentication Method
        2. 11.4.2.2 Authentication Algorithm
        3. 11.4.2.3 Update Mode
          1. 11.4.2.3.1 Overwrite
          2. 11.4.2.3.2 XIP Revert Enabled/Disabled
      3. 11.4.3 Key Update Key Hash
      4. 11.4.4 Key Ring
      5. 11.4.5 Boot Seed
    5. 11.5  Generic Image Format
    6. 11.6  Application Update
      1. 11.6.1 Image Format
    7. 11.7  Secondary Secure Bootloader Update
      1. 11.7.1 Image Format
      2. 11.7.2 Update Pattern
    8. 11.8  Key Update
      1. 11.8.1 Image Format
    9. 11.9  Antirollback
    10. 11.10 Version Log (VLOG)
      1. 11.10.1 Record structure
    11. 11.11 Fallback
    12. 11.12 ROM Panic
  14. 12General Purpose Timers (LGPT)
    1. 12.1 Overview
    2. 12.2 Block Diagram
    3. 12.3 Functional Description
      1. 12.3.1  Prescaler
      2. 12.3.2  Counter
      3. 12.3.3  Target
      4. 12.3.4  Channel Input Logic
      5. 12.3.5  Channel Output Logic
      6. 12.3.6  Channel Actions
        1. 12.3.6.1 Period and Pulse Width Measurement
        2. 12.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 12.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 12.3.7  Channel Capture Configuration
      8. 12.3.8  Channel Filters
        1. 12.3.8.1 Setting up the Channel Filters
      9. 12.3.9  Synchronize Multiple LGPT Timers
      10. 12.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 12.4 Timer Modes
      1. 12.4.1 Quadrature Decoder
      2. 12.4.2 DMA
      3. 12.4.3 IR Generation
      4. 12.4.4 Fault and Park
      5. 12.4.5 Deadband
      6. 12.4.6 Deadband, Fault, and Park
      7. 12.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 12.5 LGPT0 Registers
    6. 12.6 LGPT1 Registers
    7. 12.7 LGPT2 Registers
    8. 12.8 LGPT3 Registers
  15. 13Algorithm Processing Unit (APU)
    1. 13.1 Introduction
    2. 13.2 APU Related Collateral
    3. 13.3 Functional Description
    4. 13.4 APU Operation
    5. 13.5 Interrupts and Events
    6. 13.6 Data Representation
    7. 13.7 Data Memory
    8. 13.8 Software
    9. 13.9 APU Registers
  16. 14Voltage Glitch Monitor (VGM)
    1. 14.1 Overview
    2. 14.2 Features and Operation
  17. 15System Timer (SYSTIM)
    1. 15.1 Overview
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1 Common Channel Features
        1. 15.3.1.1 Compare Mode
        2. 15.3.1.2 Capture Mode
        3. 15.3.1.3 Additional Channel Arming Methods
      2. 15.3.2 Interrupts and Events
    4. 15.4 SYSTIM Registers
  18. 16Real Time Clock (RTC)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Interrupts and Events
      1. 16.3.1 Input Event
      2. 16.3.2 Output Event
      3. 16.3.3 Arming and Disarming Channels
    4. 16.4 CAPTURE and COMPARE Configurations
      1. 16.4.1 CHANNEL 0 - COMPARE CHANNEL
      2. 16.4.2 CHANNEL 1—CAPTURE CHANNEL
    5. 16.5 RTC Registers
  19. 17Low Power Comparator (SYS0)
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 Input Selection
      2. 17.3.2 Voltage Divider
      3. 17.3.3 Hysteresis
      4. 17.3.4 Wake-Up
    4. 17.4 SYS0 Registers
  20. 18Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 18.1 Introduction
    2. 18.2 Functional Description
      1. 18.2.1 BATMON
      2. 18.2.2 DCDC
    3. 18.3 PMUD Registers
  21. 19Micro Direct Memory Access (µDMA)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1  Channel Assignments
      2. 19.3.2  Priority
      3. 19.3.3  Arbitration Size
      4. 19.3.4  Request Types
        1. 19.3.4.1 Single Request
        2. 19.3.4.2 Burst Request
      5. 19.3.5  Channel Configuration
      6. 19.3.6  Transfer Modes
        1. 19.3.6.1 Stop Mode
        2. 19.3.6.2 Basic Mode
        3. 19.3.6.3 Auto Mode
        4. 19.3.6.4 Ping-Pong Mode
        5. 19.3.6.5 Memory Scatter-Gather Mode
        6. 19.3.6.6 Peripheral Scatter-Gather Mode
      7. 19.3.7  Transfer Size and Increments
      8. 19.3.8  Peripheral Interface
      9. 19.3.9  Software Request
      10. 19.3.10 Interrupts and Errors
      11. 19.3.11 Initialization and Configuration
        1. 19.3.11.1 Module Initialization
        2. 19.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 19.3.11.3 Configure the Channel Attributes
        4. 19.3.11.4 Configure the Channel Control Structure
        5. 19.3.11.5 Start the Transfer
        6. 19.3.11.6 Software Considerations
    4. 19.4 DMA Registers
  22. 20Advanced Encryption Standard (AES)
    1. 20.1 Introduction
      1. 20.1.1 AES Performance
    2. 20.2 Functional Description
      1. 20.2.1 Reset Considerations
      2. 20.2.2 Interrupt and Event Support
        1. 20.2.2.1 Interrupt Events and Requests
        2. 20.2.2.2 Connection to Event Fabric
      3. 20.2.3 µDMA
        1. 20.2.3.1 µDMA Example
    3. 20.3 Encryption and Decryption Configuration
      1. 20.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 20.3.2  CBC (Cipher Block Chaining) Encryption
      3. 20.3.3  CBC Decryption
      4. 20.3.4  CTR (Counter) Encryption/Decryption
      5. 20.3.5  ECB (Electronic Code Book) Encryption
      6. 20.3.6  ECB Decryption
      7. 20.3.7  CFB (Cipher Feedback) Encryption
      8. 20.3.8  CFB Decryption
      9. 20.3.9  OFB (Open Feedback) Encryption
      10. 20.3.10 OFB Decryption
      11. 20.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 20.3.12 PCBC Decryption
      13. 20.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 20.3.14 CCM
    4. 20.4 AES Registers
    5. 20.5 CRYPTO Registers
  23. 21Analog to Digital Converter (ADC)
    1. 21.1 Overview
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1  ADC Core
      2. 21.3.2  Voltage Reference Options
      3. 21.3.3  Resolution Modes
      4. 21.3.4  ADC Clocking
      5. 21.3.5  Power Down Behavior
      6. 21.3.6  Sampling Trigger Sources and Sampling Modes
        1. 21.3.6.1 AUTO Sampling Mode
        2. 21.3.6.2 MANUAL Sampling Mode
      7. 21.3.7  Sampling Period
      8. 21.3.8  Conversion Modes
      9. 21.3.9  ADC Data Format
      10. 21.3.10 Status Register
      11. 21.3.11 ADC Events
        1. 21.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 21.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 21.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 21.3.11.4 Generic Event Subscriber
    4. 21.4 Advanced Features
      1. 21.4.1 Window Comparator
      2. 21.4.2 DMA & FIFO Operation
        1. 21.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 21.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 21.4.2.3 DMA/CPU Operation Summary Matrix
      3. 21.4.3 Ad-hoc Single Conversion
    5. 21.5 ADC Registers
  24. 22I/O Controller (IOC)
    1. 22.1  Introduction
    2. 22.2  Block Diagram
    3. 22.3  I/O Mapping and Configuration
      1. 22.3.1 Basic I/O Mapping
      2. 22.3.2 Radio GPO
      3. 22.3.3 Pin Mapping
      4. 22.3.4 DTB Muxing
    4. 22.4  Edge Detection
    5. 22.5  GPIO
    6. 22.6  I/O Pins
    7. 22.7  Unused Pins
    8. 22.8  Debug Configuration
    9. 22.9  IOC Registers
    10. 22.10 GPIO Registers
  25. 23Universal Asynchronous Receiver/Transmitter (UART-LIN)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 UART Functional Description
      1. 23.3.1 Transmit and Receive Logic
      2. 23.3.2 Baud Rate Generation
      3. 23.3.3 FIFO Operation
        1. 23.3.3.1 FIFO Remapping
      4. 23.3.4 Data Transmission
      5. 23.3.5 Flow Control
      6. 23.3.6 IrDA Encoding and Decoding
      7. 23.3.7 Interrupts
      8. 23.3.8 Loopback Operation
    4. 23.4 UART-LIN Specification
      1. 23.4.1 Break transmission in UART mode
      2. 23.4.2 Break reception in UART mode
      3. 23.4.3 Break/Synch transmission in LIN mode
      4. 23.4.4 Break/Synch reception in LIN mode
      5. 23.4.5 Dormant mode operation
      6. 23.4.6 Wakeup signal generation
      7. 23.4.7 Wakeup signal detection when device is in active/idle modes
      8. 23.4.8 Wakeup signal detection when device is in standby mode
    5. 23.5 Interface to µDMA
    6. 23.6 Initialization and Configuration
    7. 23.7 UART Registers
  26. 24Serial Peripheral Interface (SPI)
    1. 24.1 Overview
      1. 24.1.1 Features
      2. 24.1.2 Block Diagram
    2. 24.2 Signal Description
    3. 24.3 Functional Description
      1. 24.3.1  Clock Control
      2. 24.3.2  FIFO Operation
        1. 24.3.2.1 Transmit FIFO
        2. 24.3.2.2 Repeated Transmit Operation
        3. 24.3.2.3 Receive FIFO
        4. 24.3.2.4 FIFO Flush
      3. 24.3.3  Interrupts
      4. 24.3.4  Data Format
      5. 24.3.5  Delayed Data Sampling
      6. 24.3.6  Chip Select Control
      7. 24.3.7  Command Data Control
      8. 24.3.8  Protocol Descriptions
        1. 24.3.8.1 Motorola SPI Frame Format
        2. 24.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 24.3.8.3 MICROWIRE Frame Format
      9. 24.3.9  CRC Configuration
      10. 24.3.10 Auto CRC Functionality
      11. 24.3.11 Auto Header Functionality
      12. 24.3.12 SPI Status
      13. 24.3.13 Debug Halt
    4. 24.4 µDMA Operation
    5. 24.5 Initialization and Configuration
    6. 24.6 SPI Registers
  27. 25Inter-Integrated Circuit (I2C)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Functional Description
      1. 25.3.1 Functional Overview
        1. 25.3.1.1 Start and Stop Conditions
        2. 25.3.1.2 Data Format with 7-Bit Address
        3. 25.3.1.3 Data Validity
        4. 25.3.1.4 Acknowledge
        5. 25.3.1.5 Arbitration
      2. 25.3.2 Available Speed Modes
      3. 25.3.3 Interrupts
        1. 25.3.3.1 I2C Controller Interrupts
        2. 25.3.3.2 I2C Target Interrupts
      4. 25.3.4 Loopback Operation
      5. 25.3.5 Command Sequence Flowcharts
        1. 25.3.5.1 I2C Controller Command Sequences
        2. 25.3.5.2 I2C Target Command Sequences
    4. 25.4 Initialization and Configuration
    5. 25.5 I2C Registers
  28. 26Inter-IC Sound (I2S)
    1. 26.1  Introduction
    2. 26.2  Block Diagram
    3. 26.3  Clock Architecture
    4. 26.4  Signal Descriptions
    5. 26.5  Functional Description
      1. 26.5.1 Pin Configuration
      2. 26.5.2 Serial Format Configuration
      3. 26.5.3 I2S Format Schematic
        1. 26.5.3.1 Register Configuration
      4. 26.5.4 Left-Justified (LJF)
        1. 26.5.4.1 Register Configuration
      5. 26.5.5 Right-Justified (RJF)
        1. 26.5.5.1 Register Configuration
      6. 26.5.6 DSP
        1. 26.5.6.1 Register Configuration
      7. 26.5.7 Clock Configuration
    6. 26.6  Memory Interface
      1. 26.6.1 Sample Word Length
      2. 26.6.2 Padding Mechanism
      3. 26.6.3 Channel Mapping
      4. 26.6.4 Sample Storage in Memory
      5. 26.6.5 DMA Operation
        1. 26.6.5.1 Start-Up
        2. 26.6.5.2 Operation
        3. 26.6.5.3 Shutdown
    7. 26.7  Samplestamp Generator
      1. 26.7.1 Samplestamp Counters
      2. 26.7.2 Start-Up Triggers
      3. 26.7.3 Samplestamp Capture
      4. 26.7.4 Achieving Constant Audio Latency
    8. 26.8  Error Detection
    9. 26.9  Usage
      1. 26.9.1 Start-Up Sequence
      2. 26.9.2 Shutdown Sequence
    10. 26.10 I2S Configuration Guideline
    11. 26.11 I2S Registers
  29. 27CAN-FD
    1. 27.1 Introduction
    2. 27.2 Functions
    3. 27.3 MCAN Subsystem
    4. 27.4 MCAN Functional Description
      1. 27.4.1 Operating Modes
        1. 27.4.1.1 Software Initialization
        2. 27.4.1.2 Normal Operation
        3. 27.4.1.3 CAN FD Operation
        4. 27.4.1.4 Transmitter Delay Compensation
          1. 27.4.1.4.1 Description
          2. 27.4.1.4.2 Transmitter Delay Compensation Measurement
        5. 27.4.1.5 Restricted Operation Mode
        6. 27.4.1.6 Bus Monitoring Mode
        7. 27.4.1.7 Disabled Automatic Retransmission
          1. 27.4.1.7.1 Frame Transmission in DAR Mode
        8. 27.4.1.8 Power Down (Sleep Mode)
          1. 27.4.1.8.1 MCAN Clock Stop and Wake Operations
          2. 27.4.1.8.2 MCAN Debug Suspend Operation
        9. 27.4.1.9 Test Modes
          1. 27.4.1.9.1 External Loop Back Mode
          2. 27.4.1.9.2 Internal Loop Back Mode
      2. 27.4.2 Timestamp Generation
        1. 27.4.2.1 External Timestamp Counter
        2. 27.4.2.2 Block Diagram
      3. 27.4.3 Timeout Counter
      4. 27.4.4 Rx Handling
        1. 27.4.4.1 Acceptance Filtering
          1. 27.4.4.1.1 Range Filter
          2. 27.4.4.1.2 Filter for specific IDs
          3. 27.4.4.1.3 Classic Bit Mask Filter
          4. 27.4.4.1.4 Standard Message ID Filtering
          5. 27.4.4.1.5 Extended Message ID Filtering
        2. 27.4.4.2 Rx FIFOs
          1. 27.4.4.2.1 Rx FIFO Blocking Mode
          2. 27.4.4.2.2 Rx FIFO Overwrite Mode
        3. 27.4.4.3 Dedicated Rx Buffers
          1. 27.4.4.3.1 Rx Buffer Handling
        4. 27.4.4.4 Debug on CAN Support
          1. 27.4.4.4.1 Filtering for Debug Messages
          2. 27.4.4.4.2 Debug Message Handling
      5. 27.4.5 Tx Handling
        1. 27.4.5.1 Transmit Pause
        2. 27.4.5.2 Dedicated Tx Buffers
        3. 27.4.5.3 Tx FIFO
        4. 27.4.5.4 Tx Queue
        5. 27.4.5.5 Mixed Dedicated Tx Buffers / Tx FIFO
        6. 27.4.5.6 Mixed Dedicated Tx Buffers / Tx Queue
        7. 27.4.5.7 Transmit Cancellation
        8. 27.4.5.8 Tx Event Handling
      6. 27.4.6 FIFO Acknowledge Handling
      7. 27.4.7 MCAN Message RAM
        1. 27.4.7.1 Message RAM Configuration
        2. 27.4.7.2 Rx Buffer and FIFO Element
        3. 27.4.7.3 Tx Buffer Element
        4. 27.4.7.4 Tx Event FIFO Element
        5. 27.4.7.5 Standard Message ID Filter Element
        6. 27.4.7.6 Extended Message ID Filter Element
      8. 27.4.8 Interrupt Requests
    5. 27.5 CC27xx MCAN Wrapper
    6. 27.6 MCAN Clock Enable
    7. 27.7 Additional Notes
    8. 27.8 CANFD Registers
  30. 28Radio
    1. 28.1  Introduction
    2. 28.2  Block Diagram
    3. 28.3  Overview
      1. 28.3.1 Radio Sub-Domains
      2. 28.3.2 Radio RAMs
      3. 28.3.3 Doorbell (DBELL)
        1. 28.3.3.1 Interrupts
        2. 28.3.3.2 GPIO Control
        3. 28.3.3.3 SYSTIM Interface
    4. 28.4  Radio Usage Model
      1. 28.4.1 CRC and Whitening
    5. 28.5  LRFDDBELL Registers
    6. 28.6  LRFDMDM32 Registers
    7. 28.7  LRFDPBE Registers
    8. 28.8  LRFDPBE32 Registers
    9. 28.9  LRFDRFE Registers
    10. 28.10 LRFDRFE32 Registers
    11. 28.11 LRFDRXF Registers
    12. 28.12 LRFDS2R Registers
    13. 28.13 LRFDTRC Registers
    14. 28.14 LRFDTXF Registers
  31. 29Revision History

28.9 LRFDRFE Registers

Table 28-324 lists the memory-mapped registers for the LRFDRFE registers. All register offset addresses not listed in Table 28-324 should be considered as reserved locations and the register contents should not be modified.

Table 28-324 LRFDRFE Registers
OffsetAcronymRegister NameSection
0hENABLEInternal. Only to be used through TI provided API.Section 28.9.1
4hFWSRCInternal. Only to be used through TI provided API.Section 28.9.2
8hINITInternal. Only to be used through TI provided API.Section 28.9.3
ChPDREQInternal. Only to be used through TI provided API.Section 28.9.4
10hEVT0Internal. Only to be used through TI provided API.Section 28.9.5
14hEVT1Internal. Only to be used through TI provided API.Section 28.9.6
18hEVTMSK0Internal. Only to be used through TI provided API.Section 28.9.7
1ChEVTMSK1Internal. Only to be used through TI provided API.Section 28.9.8
20hEVTCLR0Internal. Only to be used through TI provided API.Section 28.9.9
24hEVTCLR1Internal. Only to be used through TI provided API.Section 28.9.10
28hHFXTSTATInternal. Only to be used through TI provided API.Section 28.9.11
30hRFSTATEInternal. Only to be used through TI provided API.Section 28.9.12
38hSPINInternal. Only to be used through TI provided API.Section 28.9.13
48hAPIInternal. Only to be used through TI provided API.Section 28.9.14
4ChCMDPAR0Internal. Only to be used through TI provided API.Section 28.9.15
50hCMDPAR1Internal. Only to be used through TI provided API.Section 28.9.16
54hMSGBOXInternal. Only to be used through TI provided API.Section 28.9.17
58hMCEDATOUT0Internal. Only to be used through TI provided API.Section 28.9.18
5ChMCEDATIN0Internal. Only to be used through TI provided API.Section 28.9.19
60hMCECMDOUTInternal. Only to be used through TI provided API.Section 28.9.20
64hMCECMDINInternal. Only to be used through TI provided API.Section 28.9.21
68hPBEDATOUT1Internal. Only to be used through TI provided API.Section 28.9.22
6ChPBEDATOUT0Internal. Only to be used through TI provided API.Section 28.9.23
70hPBEDATIN0Internal. Only to be used through TI provided API.Section 28.9.24
74hPBECMDOUTInternal. Only to be used through TI provided API.Section 28.9.25
78hPBECMDINInternal. Only to be used through TI provided API.Section 28.9.26
7ChSTRBInternal. Only to be used through TI provided API.Section 28.9.27
84hMAGNTHRCFGInternal. Only to be used through TI provided API.Section 28.9.28
88hMAGNTHRInternal. Only to be used through TI provided API.Section 28.9.29
8ChRSSIOFFSETInternal. Only to be used through TI provided API.Section 28.9.30
90hGAINCTLInternal. Only to be used through TI provided API.Section 28.9.31
94hMAGNCTL0Internal. Only to be used through TI provided API.Section 28.9.32
98hMAGNCTL1Internal. Only to be used through TI provided API.Section 28.9.33
9ChSPARE0Internal. Only to be used through TI provided API.Section 28.9.34
A0hSPARE1Internal. Only to be used through TI provided API.Section 28.9.35
A4hSPARE2Internal. Only to be used through TI provided API.Section 28.9.36
A8hSPARE3Internal. Only to be used through TI provided API.Section 28.9.37
AChSPARE4Internal. Only to be used through TI provided API.Section 28.9.38
B0hSPARE5Internal. Only to be used through TI provided API.Section 28.9.39
B4hLNAInternal. Only to be used through TI provided API.Section 28.9.40
B8hIFAMPRFLDOInternal. Only to be used through TI provided API.Section 28.9.41
BChPA0Internal. Only to be used through TI provided API.Section 28.9.42
C0hULNAInternal. Only to be used through TI provided API.Section 28.9.43
C4hIFADC0Internal. Only to be used through TI provided API.Section 28.9.44
C8hIFADC1Internal. Only to be used through TI provided API.Section 28.9.45
CChIFADCLFInternal. Only to be used through TI provided API.Section 28.9.46
D0hIFADCQUANTInternal. Only to be used through TI provided API.Section 28.9.47
D4hIFADCALDOInternal. Only to be used through TI provided API.Section 28.9.48
D8hIFADCDLDOInternal. Only to be used through TI provided API.Section 28.9.49
DChIFADCTSTInternal. Only to be used through TI provided API.Section 28.9.50
E0hATSTREFLInternal. Only to be used through TI provided API.Section 28.9.51
E4hATSTREFHInternal. Only to be used through TI provided API.Section 28.9.52
E8hDCOInternal. Only to be used through TI provided API.Section 28.9.53
EChDIVInternal. Only to be used through TI provided API.Section 28.9.54
F0hDIVLDOInternal. Only to be used through TI provided API.Section 28.9.55
F4hTDCLDOInternal. Only to be used through TI provided API.Section 28.9.56
F8hDCOLDO0Internal. Only to be used through TI provided API.Section 28.9.57
FChDCOLDO1Internal. Only to be used through TI provided API.Section 28.9.58
100hPRE0Internal. Only to be used through TI provided API.Section 28.9.59
104hPRE1Internal. Only to be used through TI provided API.Section 28.9.60
108hPRE2Internal. Only to be used through TI provided API.Section 28.9.61
10ChPRE3Internal. Only to be used through TI provided API.Section 28.9.62
110hCAL0Internal. Only to be used through TI provided API.Section 28.9.63
114hCAL1Internal. Only to be used through TI provided API.Section 28.9.64
118hCAL2Internal. Only to be used through TI provided API.Section 28.9.65
11ChCAL3Internal. Only to be used through TI provided API.Section 28.9.66
120hMISC0Internal. Only to be used through TI provided API.Section 28.9.67
124hMISC1Internal. Only to be used through TI provided API.Section 28.9.68
128hLF0Internal. Only to be used through TI provided API.Section 28.9.69
12ChLF1Internal. Only to be used through TI provided API.Section 28.9.70
130hPHEDISCInternal. Only to be used through TI provided API.Section 28.9.71
134hPHINITInternal. Only to be used through TI provided API.Section 28.9.72
138hPLLMON0Internal. Only to be used through TI provided API.Section 28.9.73
13ChPLLMON1Internal. Only to be used through TI provided API.Section 28.9.74
140hMOD0Internal. Only to be used through TI provided API.Section 28.9.75
144hMOD1Internal. Only to be used through TI provided API.Section 28.9.76
148hDTX0Internal. Only to be used through TI provided API.Section 28.9.77
14ChDTX1Internal. Only to be used through TI provided API.Section 28.9.78
150hDTX2Internal. Only to be used through TI provided API.Section 28.9.79
154hDTX3Internal. Only to be used through TI provided API.Section 28.9.80
158hDTX4Internal. Only to be used through TI provided API.Section 28.9.81
15ChDTX5Internal. Only to be used through TI provided API.Section 28.9.82
160hDTX6Internal. Only to be used through TI provided API.Section 28.9.83
164hDTX7Internal. Only to be used through TI provided API.Section 28.9.84
168hDTX8Internal. Only to be used through TI provided API.Section 28.9.85
16ChDTX9Internal. Only to be used through TI provided API.Section 28.9.86
170hDTX10Internal. Only to be used through TI provided API.Section 28.9.87
174hDTX11Internal. Only to be used through TI provided API.Section 28.9.88
178hPLLM0LInternal. Only to be used through TI provided API.Section 28.9.89
17ChPLLM0HInternal. Only to be used through TI provided API.Section 28.9.90
180hPLLM1LInternal. Only to be used through TI provided API.Section 28.9.91
184hPLLM1HInternal. Only to be used through TI provided API.Section 28.9.92
188hCALMCRSInternal. Only to be used through TI provided API.Section 28.9.93
18ChCALMMIDInternal. Only to be used through TI provided API.Section 28.9.94
190hREFDIVInternal. Only to be used through TI provided API.Section 28.9.95
198hDLOCTL0Internal. Only to be used through TI provided API.Section 28.9.96
1A0hDLOCTL1Internal. Only to be used through TI provided API.Section 28.9.97
1A8hDCOOVR0Internal. Only to be used through TI provided API.Section 28.9.98
1AChDCOOVR1Internal. Only to be used through TI provided API.Section 28.9.99
1B0hDTSTInternal. Only to be used through TI provided API.Section 28.9.100
1B4hDLOEVInternal. Only to be used through TI provided API.Section 28.9.101
1B8hDTSTRDInternal. Only to be used through TI provided API.Section 28.9.102
1C0hFDCOSPANLSBInternal. Only to be used through TI provided API.Section 28.9.103
1C4hFDCOSPANMSBInternal. Only to be used through TI provided API.Section 28.9.104
1C8hTDCCALInternal. Only to be used through TI provided API.Section 28.9.105
1CChTDCCALLOWInternal. Only to be used through TI provided API.Section 28.9.106
1D0hTDCCALHIGHInternal. Only to be used through TI provided API.Section 28.9.107
1D4hTDCODETInternal. Only to be used through TI provided API.Section 28.9.108
1D8hCALRESInternal. Only to be used through TI provided API.Section 28.9.109
1DChGPIInternal. Only to be used through TI provided API.Section 28.9.110
1E0hMATHACCELINInternal. Only to be used through TI provided API.Section 28.9.111
1E4hLIN2LOGOUTInternal. Only to be used through TI provided API.Section 28.9.112
1E8hDIVBY3OUTInternal. Only to be used through TI provided API.Section 28.9.113
1EChTIMCTLInternal. Only to be used through TI provided API.Section 28.9.114
1F0hTIMINCInternal. Only to be used through TI provided API.Section 28.9.115
1F4hTIMPERInternal. Only to be used through TI provided API.Section 28.9.116
1F8hTIMCNTInternal. Only to be used through TI provided API.Section 28.9.117
1FChTIMCAPTInternal. Only to be used through TI provided API.Section 28.9.118
200hTRCCTRLInternal. Only to be used through TI provided API.Section 28.9.119
204hTRCSTATInternal. Only to be used through TI provided API.Section 28.9.120
208hTRCCMDInternal. Only to be used through TI provided API.Section 28.9.121
20ChTRCPAR0Internal. Only to be used through TI provided API.Section 28.9.122
210hTRCPAR1Internal. Only to be used through TI provided API.Section 28.9.123
214hGPOCTLInternal. Only to be used through TI provided API.Section 28.9.124
218hANAISOCTLInternal. Only to be used through TI provided API.Section 28.9.125
21ChDIVCTLInternal. Only to be used through TI provided API.Section 28.9.126
220hRXCTRLInternal. Only to be used through TI provided API.Section 28.9.127
224hMAGNACC0Internal. Only to be used through TI provided API.Section 28.9.128
228hMAGNACC1Internal. Only to be used through TI provided API.Section 28.9.129
22ChRSSIInternal. Only to be used through TI provided API.Section 28.9.130
230hRSSIMAXInternal. Only to be used through TI provided API.Section 28.9.131
234hRFGAINInternal. Only to be used through TI provided API.Section 28.9.132
238hIFADCSTATInternal. Only to be used through TI provided API.Section 28.9.133
23ChDIVSTAInternal. Only to be used through TI provided API.Section 28.9.134
240hDIVIDENDLInternal. Only to be used through TI provided API.Section 28.9.135
244hDIVIDENDHInternal. Only to be used through TI provided API.Section 28.9.136
248hDIVISORLInternal. Only to be used through TI provided API.Section 28.9.137
24ChDIVISORHInternal. Only to be used through TI provided API.Section 28.9.138
250hQUOTIENTLInternal. Only to be used through TI provided API.Section 28.9.139
254hQUOTIENTHInternal. Only to be used through TI provided API.Section 28.9.140
258hPRODUCTLInternal. Only to be used through TI provided API.Section 28.9.141
25ChPRODUCTHInternal. Only to be used through TI provided API.Section 28.9.142
260hMULTSTAInternal. Only to be used through TI provided API.Section 28.9.143
268hMULTCFGInternal. Only to be used through TI provided API.Section 28.9.144
26ChPA1Internal. Only to be used through TI provided API.Section 28.9.145
270hPA2Internal. Only to be used through TI provided API.Section 28.9.146

Complex bit access types are encoded to fit into small table cells. Table 28-325 shows the codes that are used for access types in this section.

Table 28-325 LRFDRFE Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

28.9.1 ENABLE Register (Offset = 0h) [Reset = 00000000h]

ENABLE is shown in Table 28-326.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-326 ENABLE Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3ACC1R/W0hInternal. Only to be used through TI provided API.
2ACC0R/W0hInternal. Only to be used through TI provided API.
1LOCTIMR/W0hInternal. Only to be used through TI provided API.
0TOPSMR/W0hInternal. Only to be used through TI provided API.

28.9.2 FWSRC Register (Offset = 4h) [Reset = 00000000h]

FWSRC is shown in Table 28-327.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-327 FWSRC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2DATARAMR/W0hInternal. Only to be used through TI provided API.
1FWRAMR/W0hInternal. Only to be used through TI provided API.
0BANKR/W0hInternal. Only to be used through TI provided API.

28.9.3 INIT Register (Offset = 8h) [Reset = 00000000h]

INIT is shown in Table 28-328.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-328 INIT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3ACC1W0hInternal. Only to be used through TI provided API.
2ACC0W0hInternal. Only to be used through TI provided API.
1LOCTIMW0hInternal. Only to be used through TI provided API.
0TOPSMW0hInternal. Only to be used through TI provided API.

28.9.4 PDREQ Register (Offset = Ch) [Reset = 00000000h]

PDREQ is shown in Table 28-329.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-329 PDREQ Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0TOPSMPDREQR/W0hInternal. Only to be used through TI provided API.

28.9.5 EVT0 Register (Offset = 10h) [Reset = 00000000h]

EVT0 is shown in Table 28-330.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-330 EVT0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14MAGNTHRR0hInternal. Only to be used through TI provided API.
13S2RSTOPR0hInternal. Only to be used through TI provided API.
12SYSTCMP2R0hInternal. Only to be used through TI provided API.
11SYSTCMP1R0hInternal. Only to be used through TI provided API.
10SYSTCMP0R0hInternal. Only to be used through TI provided API.
9PBERFEDATR0hInternal. Only to be used through TI provided API.
8MDMRFEDATR0hInternal. Only to be used through TI provided API.
7DLOR0hInternal. Only to be used through TI provided API.
6PBECMDR0hInternal. Only to be used through TI provided API.
5COUNTERR0hInternal. Only to be used through TI provided API.
4MDMCMDR0hInternal. Only to be used through TI provided API.
3ACC1R0hInternal. Only to be used through TI provided API.
2ACC0R0hInternal. Only to be used through TI provided API.
1TIMERR0hInternal. Only to be used through TI provided API.
0RFEAPIR0hInternal. Only to be used through TI provided API.

28.9.6 EVT1 Register (Offset = 14h) [Reset = 00000000h]

EVT1 is shown in Table 28-331.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-331 EVT1 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13PREREFCLKR0hInternal. Only to be used through TI provided API.
12REFCLKR0hInternal. Only to be used through TI provided API.
11FBLWTHRR0hInternal. Only to be used through TI provided API.
10FABVTHRR0hInternal. Only to be used through TI provided API.
9LOCKR0hInternal. Only to be used through TI provided API.
8LOLR0hInternal. Only to be used through TI provided API.
7GPI7R0hInternal. Only to be used through TI provided API.
6GPI6R0hInternal. Only to be used through TI provided API.
5GPI5R0hInternal. Only to be used through TI provided API.
4GPI4R0hInternal. Only to be used through TI provided API.
3GPI3R0hInternal. Only to be used through TI provided API.
2GPI2R0hInternal. Only to be used through TI provided API.
1GPI1R0hInternal. Only to be used through TI provided API.
0GPI0R0hInternal. Only to be used through TI provided API.

28.9.7 EVTMSK0 Register (Offset = 18h) [Reset = 00000000h]

EVTMSK0 is shown in Table 28-332.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-332 EVTMSK0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14MAGNTHRR/W0hInternal. Only to be used through TI provided API.
13S2RSTOPR/W0hInternal. Only to be used through TI provided API.
12SYSTCMP2R/W0hInternal. Only to be used through TI provided API.
11SYSTCMP1R/W0hInternal. Only to be used through TI provided API.
10SYSTCMP0R/W0hInternal. Only to be used through TI provided API.
9PBERFEDATR/W0hInternal. Only to be used through TI provided API.
8MDMRFEDATR/W0hInternal. Only to be used through TI provided API.
7DLOR/W0hInternal. Only to be used through TI provided API.
6PBECMDR/W0hInternal. Only to be used through TI provided API.
5COUNTERR/W0hInternal. Only to be used through TI provided API.
4MDMCMDR/W0hInternal. Only to be used through TI provided API.
3ACC1R/W0hInternal. Only to be used through TI provided API.
2ACC0R/W0hInternal. Only to be used through TI provided API.
1TIMERR/W0hInternal. Only to be used through TI provided API.
0RFEAPIR/W0hInternal. Only to be used through TI provided API.

28.9.8 EVTMSK1 Register (Offset = 1Ch) [Reset = 00000000h]

EVTMSK1 is shown in Table 28-333.

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Internal. Only to be used through TI provided API.

Table 28-333 EVTMSK1 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13PREREFCLKR/W0hInternal. Only to be used through TI provided API.
12REFCLKR/W0hInternal. Only to be used through TI provided API.
11FBLWTHRR/W0hInternal. Only to be used through TI provided API.
10FABVTHRR/W0hInternal. Only to be used through TI provided API.
9LOCKR/W0hInternal. Only to be used through TI provided API.
8LOLR/W0hInternal. Only to be used through TI provided API.
7GPI7R/W0hInternal. Only to be used through TI provided API.
6GPI6R/W0hInternal. Only to be used through TI provided API.
5GPI5R/W0hInternal. Only to be used through TI provided API.
4GPI4R/W0hInternal. Only to be used through TI provided API.
3GPI3R/W0hInternal. Only to be used through TI provided API.
2GPI2R/W0hInternal. Only to be used through TI provided API.
1GPI1R/W0hInternal. Only to be used through TI provided API.
0GPI0R/W0hInternal. Only to be used through TI provided API.

28.9.9 EVTCLR0 Register (Offset = 20h) [Reset = 00000000h]

EVTCLR0 is shown in Table 28-334.

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Internal. Only to be used through TI provided API.

Table 28-334 EVTCLR0 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14MAGNTHRW0hInternal. Only to be used through TI provided API.
13S2RSTOPW0hInternal. Only to be used through TI provided API.
12SYSTCMP2W0hInternal. Only to be used through TI provided API.
11SYSTCMP1W0hInternal. Only to be used through TI provided API.
10SYSTCMP0W0hInternal. Only to be used through TI provided API.
9PBERFEDATW0hInternal. Only to be used through TI provided API.
8MDMRFEDATW0hInternal. Only to be used through TI provided API.
7DLOW0hInternal. Only to be used through TI provided API.
6PBECMDW0hInternal. Only to be used through TI provided API.
5COUNTERW0hInternal. Only to be used through TI provided API.
4MDMCMDW0hInternal. Only to be used through TI provided API.
3ACC1W0hInternal. Only to be used through TI provided API.
2ACC0W0hInternal. Only to be used through TI provided API.
1TIMERW0hInternal. Only to be used through TI provided API.
0RFEAPIW0hInternal. Only to be used through TI provided API.

28.9.10 EVTCLR1 Register (Offset = 24h) [Reset = 00000000h]

EVTCLR1 is shown in Table 28-335.

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Internal. Only to be used through TI provided API.

Table 28-335 EVTCLR1 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13PREREFCLKW0hInternal. Only to be used through TI provided API.
12REFCLKW0hInternal. Only to be used through TI provided API.
11FBLWTHRW0hInternal. Only to be used through TI provided API.
10FABVTHRW0hInternal. Only to be used through TI provided API.
9LOCKW0hInternal. Only to be used through TI provided API.
8LOLW0hInternal. Only to be used through TI provided API.
7GPI7W0hInternal. Only to be used through TI provided API.
6GPI6W0hInternal. Only to be used through TI provided API.
5GPI5W0hInternal. Only to be used through TI provided API.
4GPI4W0hInternal. Only to be used through TI provided API.
3GPI3W0hInternal. Only to be used through TI provided API.
2GPI2W0hInternal. Only to be used through TI provided API.
1GPI1W0hInternal. Only to be used through TI provided API.
0GPI0W0hInternal. Only to be used through TI provided API.

28.9.11 HFXTSTAT Register (Offset = 28h) [Reset = 00000000h]

HFXTSTAT is shown in Table 28-336.

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Internal. Only to be used through TI provided API.

Table 28-336 HFXTSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STATR0hInternal. Only to be used through TI provided API.

28.9.12 RFSTATE Register (Offset = 30h) [Reset = 00000000h]

RFSTATE is shown in Table 28-337.

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Internal. Only to be used through TI provided API.

Table 28-337 RFSTATE Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.13 SPIN Register (Offset = 38h) [Reset = 00000000h]

SPIN is shown in Table 28-338.

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Internal. Only to be used through TI provided API.

Table 28-338 SPIN Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0OPTRFFhInternal. Only to be used through TI provided API.

28.9.14 API Register (Offset = 48h) [Reset = 00000000h]

API is shown in Table 28-339.

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Internal. Only to be used through TI provided API.

Table 28-339 API Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-4PROTOCOLIDR0hInternal. Only to be used through TI provided API.
3-0RFECMDR0hInternal. Only to be used through TI provided API.

28.9.15 CMDPAR0 Register (Offset = 4Ch) [Reset = 00000000h]

CMDPAR0 is shown in Table 28-340.

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Internal. Only to be used through TI provided API.

Table 28-340 CMDPAR0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.16 CMDPAR1 Register (Offset = 50h) [Reset = 00000000h]

CMDPAR1 is shown in Table 28-341.

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Internal. Only to be used through TI provided API.

Table 28-341 CMDPAR1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.17 MSGBOX Register (Offset = 54h) [Reset = 00000000h]

MSGBOX is shown in Table 28-342.

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Internal. Only to be used through TI provided API.

Table 28-342 MSGBOX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.18 MCEDATOUT0 Register (Offset = 58h) [Reset = 00000000h]

MCEDATOUT0 is shown in Table 28-343.

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Internal. Only to be used through TI provided API.

Table 28-343 MCEDATOUT0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.19 MCEDATIN0 Register (Offset = 5Ch) [Reset = 00000000h]

MCEDATIN0 is shown in Table 28-344.

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Internal. Only to be used through TI provided API.

Table 28-344 MCEDATIN0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.20 MCECMDOUT Register (Offset = 60h) [Reset = 00000000h]

MCECMDOUT is shown in Table 28-345.

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Internal. Only to be used through TI provided API.

Table 28-345 MCECMDOUT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.21 MCECMDIN Register (Offset = 64h) [Reset = 00000000h]

MCECMDIN is shown in Table 28-346.

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Internal. Only to be used through TI provided API.

Table 28-346 MCECMDIN Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VALR0hInternal. Only to be used through TI provided API.

28.9.22 PBEDATOUT1 Register (Offset = 68h) [Reset = 00000000h]

PBEDATOUT1 is shown in Table 28-347.

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Internal. Only to be used through TI provided API.

Table 28-347 PBEDATOUT1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.23 PBEDATOUT0 Register (Offset = 6Ch) [Reset = 00000000h]

PBEDATOUT0 is shown in Table 28-348.

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Internal. Only to be used through TI provided API.

Table 28-348 PBEDATOUT0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.24 PBEDATIN0 Register (Offset = 70h) [Reset = 00000000h]

PBEDATIN0 is shown in Table 28-349.

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Internal. Only to be used through TI provided API.

Table 28-349 PBEDATIN0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.25 PBECMDOUT Register (Offset = 74h) [Reset = 00000000h]

PBECMDOUT is shown in Table 28-350.

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Internal. Only to be used through TI provided API.

Table 28-350 PBECMDOUT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.26 PBECMDIN Register (Offset = 78h) [Reset = 00000000h]

PBECMDIN is shown in Table 28-351.

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Internal. Only to be used through TI provided API.

Table 28-351 PBECMDIN Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0VALR0hInternal. Only to be used through TI provided API.

28.9.27 STRB Register (Offset = 7Ch) [Reset = 00000000h]

STRB is shown in Table 28-352.

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Internal. Only to be used through TI provided API.

Table 28-352 STRB Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7S2RTRGW0hInternal. Only to be used through TI provided API.
6DMATRGW0hInternal. Only to be used through TI provided API.
5SYSTCPT2W0hInternal. Only to be used through TI provided API.
4SYSTCPT1W0hInternal. Only to be used through TI provided API.
3SYSTCPT0W0hInternal. Only to be used through TI provided API.
2EVT1W0hInternal. Only to be used through TI provided API.
1EVT0W0hInternal. Only to be used through TI provided API.
0CMDDONEW0hInternal. Only to be used through TI provided API.

28.9.28 MAGNTHRCFG Register (Offset = 84h) [Reset = 00000000h]

MAGNTHRCFG is shown in Table 28-353.

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Internal. Only to be used through TI provided API.

Table 28-353 MAGNTHRCFG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1SELR/W0hInternal. Only to be used through TI provided API.
0CTLR/W0hInternal. Only to be used through TI provided API.

28.9.29 MAGNTHR Register (Offset = 88h) [Reset = 00000000h]

MAGNTHR is shown in Table 28-354.

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Internal. Only to be used through TI provided API.

Table 28-354 MAGNTHR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.30 RSSIOFFSET Register (Offset = 8Ch) [Reset = 00000000h]

RSSIOFFSET is shown in Table 28-355.

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Internal. Only to be used through TI provided API.

Table 28-355 RSSIOFFSET Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.31 GAINCTL Register (Offset = 90h) [Reset = 00000000h]

GAINCTL is shown in Table 28-356.

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Internal. Only to be used through TI provided API.

Table 28-356 GAINCTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2BDE2DVGAR/W0hInternal. Only to be used through TI provided API.
1-0BDE1DVGAR/W0hInternal. Only to be used through TI provided API.

28.9.32 MAGNCTL0 Register (Offset = 94h) [Reset = 00000000h]

MAGNCTL0 is shown in Table 28-357.

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Internal. Only to be used through TI provided API.

Table 28-357 MAGNCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12PERMODER/W0hInternal. Only to be used through TI provided API.
11-8SCLR/W0hInternal. Only to be used through TI provided API.
7-0PERR/W0hInternal. Only to be used through TI provided API.

28.9.33 MAGNCTL1 Register (Offset = 98h) [Reset = 00000000h]

MAGNCTL1 is shown in Table 28-358.

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Internal. Only to be used through TI provided API.

Table 28-358 MAGNCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12PERMODER/W0hInternal. Only to be used through TI provided API.
11-8SCLR/W0hInternal. Only to be used through TI provided API.
7-0PERR/W0hInternal. Only to be used through TI provided API.

28.9.34 SPARE0 Register (Offset = 9Ch) [Reset = 00000000h]

SPARE0 is shown in Table 28-359.

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Internal. Only to be used through TI provided API.

Table 28-359 SPARE0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.35 SPARE1 Register (Offset = A0h) [Reset = 00000000h]

SPARE1 is shown in Table 28-360.

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Internal. Only to be used through TI provided API.

Table 28-360 SPARE1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.36 SPARE2 Register (Offset = A4h) [Reset = 00000000h]

SPARE2 is shown in Table 28-361.

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Internal. Only to be used through TI provided API.

Table 28-361 SPARE2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.37 SPARE3 Register (Offset = A8h) [Reset = 00000000h]

SPARE3 is shown in Table 28-362.

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Internal. Only to be used through TI provided API.

Table 28-362 SPARE3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.38 SPARE4 Register (Offset = ACh) [Reset = 00000000h]

SPARE4 is shown in Table 28-363.

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Internal. Only to be used through TI provided API.

Table 28-363 SPARE4 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.39 SPARE5 Register (Offset = B0h) [Reset = 00000000h]

SPARE5 is shown in Table 28-364.

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Internal. Only to be used through TI provided API.

Table 28-364 SPARE5 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.40 LNA Register (Offset = B4h) [Reset = 00000000h]

LNA is shown in Table 28-365.

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Internal. Only to be used through TI provided API.

Table 28-365 LNA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-13SPARER/W0hInternal. Only to be used through TI provided API.
12PA20DBMATSTSELR/W0hInternal. Only to be used through TI provided API.
11PA20DBMATSTR/W0hInternal. Only to be used through TI provided API.
10MIXATSTR/W0hInternal. Only to be used through TI provided API.
9LDOITSTR/W0hInternal. Only to be used through TI provided API.
8LDOATSTR/W0hInternal. Only to be used through TI provided API.
7-4TRIMR/W0hInternal. Only to be used through TI provided API.
3MIXCAPR/W0hInternal. Only to be used through TI provided API.
2-1IBR/W0hInternal. Only to be used through TI provided API.
0ENR/W0hInternal. Only to be used through TI provided API.

28.9.41 IFAMPRFLDO Register (Offset = B8h) [Reset = 00000000h]

IFAMPRFLDO is shown in Table 28-366.

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Internal. Only to be used through TI provided API.

Table 28-366 IFAMPRFLDO Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-9TRIMR/W0hInternal. Only to be used through TI provided API.
8ENR/W0hInternal. Only to be used through TI provided API.
7-4AAFCAPR/W0hInternal. Only to be used through TI provided API.
3-1IFAMPIBR/W0hInternal. Only to be used through TI provided API.
0IFAMPR/W0hInternal. Only to be used through TI provided API.

28.9.42 PA0 Register (Offset = BCh) [Reset = 00000000h]

PA0 is shown in Table 28-367.

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Internal. Only to be used through TI provided API.

Table 28-367 PA0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14SPARE14R/W0hInternal. Only to be used through TI provided API.
13BIASSELR/W0hInternal. Only to be used through TI provided API.
12PA20DBMESDCTLR/W0hInternal. Only to be used through TI provided API.
11-9VCADJSCNDR/W0hInternal. Only to be used through TI provided API.
8-6VCADJFRSTR/W0hInternal. Only to be used through TI provided API.
5-4RCR/W0hInternal. Only to be used through TI provided API.
3-2SPARE2R/W0hInternal. Only to be used through TI provided API.
1RAMPR/W0hInternal. Only to be used through TI provided API.
0ENR/W0hInternal. Only to be used through TI provided API.

28.9.43 ULNA Register (Offset = C0h) [Reset = 00000000h]

ULNA is shown in Table 28-368.

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Internal. Only to be used through TI provided API.

Table 28-368 ULNA Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0SPARER/W0hInternal. Only to be used through TI provided API.

28.9.44 IFADC0 Register (Offset = C4h) [Reset = 00000000h]

IFADC0 is shown in Table 28-369.

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Internal. Only to be used through TI provided API.

Table 28-369 IFADC0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15EXTCLKR/W0hInternal. Only to be used through TI provided API.
14-12DITHERTRIMR/W0hInternal. Only to be used through TI provided API.
11-10DITHERENR/W0hInternal. Only to be used through TI provided API.
9ADCIENR/W0hInternal. Only to be used through TI provided API.
8ADCQENR/W0hInternal. Only to be used through TI provided API.
7-4INT2ADJR/W0hInternal. Only to be used through TI provided API.
3-2AAFCAPR/W0hInternal. Only to be used through TI provided API.
1-0RESERVEDR0hInternal. Only to be used through TI provided API.

28.9.45 IFADC1 Register (Offset = C8h) [Reset = 00000000h]

IFADC1 is shown in Table 28-370.

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Internal. Only to be used through TI provided API.

Table 28-370 IFADC1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15NRZR/W0hInternal. Only to be used through TI provided API.
14-9TRIMR/W0hInternal. Only to be used through TI provided API.
8RESERVEDR0hInternal. Only to be used through TI provided API.
7RSTNR/W0hInternal. Only to be used through TI provided API.
6CLKGENR/W0hInternal. Only to be used through TI provided API.
5ADCDIGCLKR/W0hInternal. Only to be used through TI provided API.
4ADCLFSROUTR/W0hInternal. Only to be used through TI provided API.
3-1LPFTSTMODER/W0hInternal. Only to be used through TI provided API.
0INVCLKOUTR/W0hInternal. Only to be used through TI provided API.

28.9.46 IFADCLF Register (Offset = CCh) [Reset = 00000000h]

IFADCLF is shown in Table 28-371.

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Internal. Only to be used through TI provided API.

Table 28-371 IFADCLF Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-12FF3R/W0hInternal. Only to be used through TI provided API.
11-8FF2R/W0hInternal. Only to be used through TI provided API.
7-4FF1R/W0hInternal. Only to be used through TI provided API.
3-0INT3R/W0hInternal. Only to be used through TI provided API.

28.9.47 IFADCQUANT Register (Offset = D0h) [Reset = 00000000h]

IFADCQUANT is shown in Table 28-372.

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Internal. Only to be used through TI provided API.

Table 28-372 IFADCQUANT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14CLKDLYTRIMR/W0hInternal. Only to be used through TI provided API.
13-9DBGCALVALINR/W0hInternal. Only to be used through TI provided API.
8DBGCALLEGR/W0hInternal. Only to be used through TI provided API.
7-6DBGCALMQR/W0hInternal. Only to be used through TI provided API.
5-4DBGCALMIR/W0hInternal. Only to be used through TI provided API.
3AUTOCALR/W0hInternal. Only to be used through TI provided API.
2-0QUANTTHRR/W0hInternal. Only to be used through TI provided API.

28.9.48 IFADCALDO Register (Offset = D4h) [Reset = 00000000h]

IFADCALDO is shown in Table 28-373.

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Internal. Only to be used through TI provided API.

Table 28-373 IFADCALDO Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15ATESTVSSANAR/W0hInternal. Only to be used through TI provided API.
14RESERVEDR0hInternal. Only to be used through TI provided API.
13-8TRIMOUTR/W0hInternal. Only to be used through TI provided API.
7DUMMYR/W0hInternal. Only to be used through TI provided API.
6ATESTERRAMPR/W0hInternal. Only to be used through TI provided API.
5ATESTINPUTREFR/W0hInternal. Only to be used through TI provided API.
4ATESTOUTR/W0hInternal. Only to be used through TI provided API.
3ITESTR/W0hInternal. Only to be used through TI provided API.
2BYPASSR/W0hInternal. Only to be used through TI provided API.
1CLAMPR/W0hInternal. Only to be used through TI provided API.
0CTLR/W0hInternal. Only to be used through TI provided API.

28.9.49 IFADCDLDO Register (Offset = D8h) [Reset = 00000000h]

IFADCDLDO is shown in Table 28-374.

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Internal. Only to be used through TI provided API.

Table 28-374 IFADCDLDO Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14RESERVEDR0hInternal. Only to be used through TI provided API.
13-8TRIMOUTR/W0hInternal. Only to be used through TI provided API.
7SPARE7R/W0hInternal. Only to be used through TI provided API.
6ATESTERRAMPR/W0hInternal. Only to be used through TI provided API.
5ATESTFBR/W0hInternal. Only to be used through TI provided API.
4ATESTOUTR/W0hInternal. Only to be used through TI provided API.
3ITESTR/W0hInternal. Only to be used through TI provided API.
2BYPASSR/W0hInternal. Only to be used through TI provided API.
1CLAMPR/W0hInternal. Only to be used through TI provided API.
0CTLR/W0hInternal. Only to be used through TI provided API.

28.9.50 IFADCTST Register (Offset = DCh) [Reset = 00000000h]

IFADCTST is shown in Table 28-375.

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Internal. Only to be used through TI provided API.

Table 28-375 IFADCTST Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7EXTCURRR/W0hInternal. Only to be used through TI provided API.
6QCALDBIQR/W0hInternal. Only to be used through TI provided API.
5QCALDBCR/W0hInternal. Only to be used through TI provided API.
4-0SELR/W0hInternal. Only to be used through TI provided API.

28.9.51 ATSTREFL Register (Offset = E0h) [Reset = 00000000h]

ATSTREFL is shown in Table 28-376.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-376 ATSTREFL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0MUXLSBR/W0hInternal. Only to be used through TI provided API.

28.9.52 ATSTREFH Register (Offset = E4h) [Reset = 00000000h]

ATSTREFH is shown in Table 28-377.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-377 ATSTREFH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15VREFBPDISR/W0hInternal. Only to be used through TI provided API.
14-10IREFTRIMR/W0hInternal. Only to be used through TI provided API.
9BIASR/W0hInternal. Only to be used through TI provided API.
8OUTPUT1R/W0hInternal. Only to be used through TI provided API.
7OUTPUT2R/W0hInternal. Only to be used through TI provided API.
6-0MUXMSBR/W0hInternal. Only to be used through TI provided API.

28.9.53 DCO Register (Offset = E8h) [Reset = 00000000h]

DCO is shown in Table 28-378.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-378 DCO Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-9MTDCSPARER/W0hInternal. Only to be used through TI provided API.
8-7SPARE7R/W0hInternal. Only to be used through TI provided API.
6-3TAILRESTRIMR/W0hInternal. Only to be used through TI provided API.
2RTRIMCAPR/W0hInternal. Only to be used through TI provided API.
1CNRCAPR/W0hInternal. Only to be used through TI provided API.
0CRSCAPCMR/W0hInternal. Only to be used through TI provided API.

28.9.54 DIV Register (Offset = ECh) [Reset = 00000000h]

DIV is shown in Table 28-379.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-379 DIV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15PDETR/W0hInternal. Only to be used through TI provided API.
14-12NMIREFTRIMR/W0hInternal. Only to be used through TI provided API.
11-9PMIREFTRIMR/W0hInternal. Only to be used through TI provided API.
8TXBBOOSTR/W0hInternal. Only to be used through TI provided API.
7S1GFRCR/W0hInternal. Only to be used through TI provided API.
6-5BUFGAINR/W0hInternal. Only to be used through TI provided API.
4BIASR/W0hInternal. Only to be used through TI provided API.
3OUTR/W0hInternal. Only to be used through TI provided API.
2-0RATIOR/W0hInternal. Only to be used through TI provided API.

28.9.55 DIVLDO Register (Offset = F0h) [Reset = 00000000h]

DIVLDO is shown in Table 28-380.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Table 28-380 DIVLDO Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15ITESTCTLR/W0hInternal. Only to be used through TI provided API.
14-8VOUTTRIMR/W0hInternal. Only to be used through TI provided API.
7SPARE7R/W0hInternal. Only to be used through TI provided API.
6-4TMUXR/W0hInternal. Only to be used through TI provided API.
3PDSELR/W0hInternal. Only to be used through TI provided API.
2MODER/W0hInternal. Only to be used through TI provided API.
1BYPASSR/W0hInternal. Only to be used through TI provided API.
0CTLR/W0hInternal. Only to be used through TI provided API.

28.9.56 TDCLDO Register (Offset = F4h) [Reset = 00000000h]

TDCLDO is shown in Table 28-381.

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Internal. Only to be used through TI provided API.

Table 28-381 TDCLDO Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15ITESTCTLR/W0hInternal. Only to be used through TI provided API.
14-8VOUTTRIMR/W0hInternal. Only to be used through TI provided API.
7SPARE7R/W0hInternal. Only to be used through TI provided API.
6-4TMUXR/W0hInternal. Only to be used through TI provided API.
3PDSELR/W0hInternal. Only to be used through TI provided API.
2MODER/W0hInternal. Only to be used through TI provided API.
1BYPASSR/W0hInternal. Only to be used through TI provided API.
0CTLR/W0hInternal. Only to be used through TI provided API.

28.9.57 DCOLDO0 Register (Offset = F8h) [Reset = 00000000h]

DCOLDO0 is shown in Table 28-382.

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Internal. Only to be used through TI provided API.

Table 28-382 DCOLDO0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14ITSTR/W0hInternal. Only to be used through TI provided API.
13-8SECONDTRIMR/W0hInternal. Only to be used through TI provided API.
7-4FIRSTTRIMR/W0hInternal. Only to be used through TI provided API.
3PDNR/W0hInternal. Only to be used through TI provided API.
2BYPFIRSTR/W0hInternal. Only to be used through TI provided API.
1BYPBOTHR/W0hInternal. Only to be used through TI provided API.
0CTLR/W0hInternal. Only to be used through TI provided API.

28.9.58 DCOLDO1 Register (Offset = FCh) [Reset = 00000000h]

DCOLDO1 is shown in Table 28-383.

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Internal. Only to be used through TI provided API.

Table 28-383 DCOLDO1 Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10REFSRCR/W0hInternal. Only to be used through TI provided API.
9-8DIVATSTR/W0hInternal. Only to be used through TI provided API.
7PERFMR/W0hInternal. Only to be used through TI provided API.
6CHRGFILTR/W0hInternal. Only to be used through TI provided API.
5-0ATSTR/W0hInternal. Only to be used through TI provided API.

28.9.59 PRE0 Register (Offset = 100h) [Reset = 00000000h]

PRE0 is shown in Table 28-384.

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Internal. Only to be used through TI provided API.

Table 28-384 PRE0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14SPARE14R/W0hInternal. Only to be used through TI provided API.
13-8PLLDIV1R/W0hInternal. Only to be used through TI provided API.
7-6SPARE6R/W0hInternal. Only to be used through TI provided API.
5-0PLLDIV0R/W0hInternal. Only to be used through TI provided API.

28.9.60 PRE1 Register (Offset = 104h) [Reset = 00000000h]

PRE1 is shown in Table 28-385.

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Internal. Only to be used through TI provided API.

Table 28-385 PRE1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14IIRBWR/W0hInternal. Only to be used through TI provided API.
13IIRORDR/W0hInternal. Only to be used through TI provided API.
12-8IIRDIVR/W0hInternal. Only to be used through TI provided API.
7RESERVEDR0hReserved
6CALHSDDCR/W0hInternal. Only to be used through TI provided API.
5-0HSDDCR/W0hInternal. Only to be used through TI provided API.

28.9.61 PRE2 Register (Offset = 108h) [Reset = 00000000h]

PRE2 is shown in Table 28-386.

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Internal. Only to be used through TI provided API.

Table 28-386 PRE2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-12MIDCALDIVLSBR/W0hInternal. Only to be used through TI provided API.
11-6CRSCALDIVR/W0hInternal. Only to be used through TI provided API.
5-0FSMDIVR/W0hInternal. Only to be used through TI provided API.

28.9.62 PRE3 Register (Offset = 10Ch) [Reset = 00000000h]

PRE3 is shown in Table 28-387.

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Internal. Only to be used through TI provided API.

Table 28-387 PRE3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-5FINECALDIVR/W0hInternal. Only to be used through TI provided API.
4-0MIDCALDIVMSBR/W0hInternal. Only to be used through TI provided API.

28.9.63 CAL0 Register (Offset = 110h) [Reset = 00000000h]

CAL0 is shown in Table 28-388.

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Internal. Only to be used through TI provided API.

Table 28-388 CAL0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15SPARE15R/W0hInternal. Only to be used through TI provided API.
14-8FCSTARTR/W0hInternal. Only to be used through TI provided API.
7CRSR/W0hInternal. Only to be used through TI provided API.
6MIDR/W0hInternal. Only to be used through TI provided API.
5KTDCR/W0hInternal. Only to be used through TI provided API.
4KDCOR/W0hInternal. Only to be used through TI provided API.
3-2TDCAVGR/W0hInternal. Only to be used through TI provided API.
1-0TDC_SPARER/W0hInternal. Only to be used through TI provided API.

28.9.64 CAL1 Register (Offset = 114h) [Reset = 00000000h]

CAL1 is shown in Table 28-389.

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Internal. Only to be used through TI provided API.

Table 28-389 CAL1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15SPARE15R/W0hInternal. Only to be used through TI provided API.
14-8FCTOPR/W0hInternal. Only to be used through TI provided API.
7SPARE7R/W0hInternal. Only to be used through TI provided API.
6-0FCBOTR/W0hInternal. Only to be used through TI provided API.

28.9.65 CAL2 Register (Offset = 118h) [Reset = 00000000h]

CAL2 is shown in Table 28-390.

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Internal. Only to be used through TI provided API.

Table 28-390 CAL2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0KTDCINVR/W0hInternal. Only to be used through TI provided API.

28.9.66 CAL3 Register (Offset = 11Ch) [Reset = 00000000h]

CAL3 is shown in Table 28-391.

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Internal. Only to be used through TI provided API.

Table 28-391 CAL3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DTXGAINR/W0hInternal. Only to be used through TI provided API.

28.9.67 MISC0 Register (Offset = 120h) [Reset = 00000000h]

MISC0 is shown in Table 28-392.

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Internal. Only to be used through TI provided API.

Table 28-392 MISC0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15TDCCALENHCTLR/W0hInternal. Only to be used through TI provided API.
14TDCCALENHCFGR/W0hInternal. Only to be used through TI provided API.
13PHCPTR/W0hInternal. Only to be used through TI provided API.
12TDCCALCORRR/W0hInternal. Only to be used through TI provided API.
11TDCMSBCORRR/W0hInternal. Only to be used through TI provided API.
10SDMDEMR/W0hInternal. Only to be used through TI provided API.
9-8DLYSDMR/W0hInternal. Only to be used through TI provided API.
7CKVDENFRCR/W0hInternal. Only to be used through TI provided API.
6DLYPHVALIDR/W0hInternal. Only to be used through TI provided API.
5-4DLYCANCRSR/W0hInternal. Only to be used through TI provided API.
3-2DLYCANFINER/W0hInternal. Only to be used through TI provided API.
1-0DLYADDR/W0hInternal. Only to be used through TI provided API.

28.9.68 MISC1 Register (Offset = 124h) [Reset = 00000000h]

MISC1 is shown in Table 28-393.

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Internal. Only to be used through TI provided API.

Table 28-393 MISC1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14FCDEMCLKR/W0hInternal. Only to be used through TI provided API.
13-12FCDEMUPDR/W0hInternal. Only to be used through TI provided API.
11-6TDCINLR/W0hInternal. Only to be used through TI provided API.
5TDCINLCTLR/W0hInternal. Only to be used through TI provided API.
4PHINITR/W0hInternal. Only to be used through TI provided API.
3SDMOOVRCTLR/W0hInternal. Only to be used through TI provided API.
2-0SDMOOVRR/W0hInternal. Only to be used through TI provided API.

28.9.69 LF0 Register (Offset = 128h) [Reset = 00000000h]

LF0 is shown in Table 28-394.

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Internal. Only to be used through TI provided API.

Table 28-394 LF0 Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12KIPRECR/W0hInternal. Only to be used through TI provided API.
11-0KIR/W0hInternal. Only to be used through TI provided API.

28.9.70 LF1 Register (Offset = 12Ch) [Reset = 00000000h]

LF1 is shown in Table 28-395.

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Internal. Only to be used through TI provided API.

Table 28-395 LF1 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-0KPR/W0hInternal. Only to be used through TI provided API.

28.9.71 PHEDISC Register (Offset = 130h) [Reset = 00000000h]

PHEDISC is shown in Table 28-396.

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Internal. Only to be used through TI provided API.

Table 28-396 PHEDISC Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-10CNTR/W0hInternal. Only to be used through TI provided API.
9-0THRR/W0hInternal. Only to be used through TI provided API.

28.9.72 PHINIT Register (Offset = 134h) [Reset = 00000000h]

PHINIT is shown in Table 28-397.

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Internal. Only to be used through TI provided API.

Table 28-397 PHINIT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0OFFR/W0hInternal. Only to be used through TI provided API.

28.9.73 PLLMON0 Register (Offset = 138h) [Reset = 00000000h]

PLLMON0 is shown in Table 28-398.

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Internal. Only to be used through TI provided API.

Table 28-398 PLLMON0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-14PHELOLCNTR/W0hInternal. Only to be used through TI provided API.
13-8PHELOLTHRR/W0hInternal. Only to be used through TI provided API.
7RESERVEDR0hReserved
6-0FCTHRR/W0hInternal. Only to be used through TI provided API.

28.9.74 PLLMON1 Register (Offset = 13Ch) [Reset = 00000000h]

PLLMON1 is shown in Table 28-399.

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Internal. Only to be used through TI provided API.

Table 28-399 PLLMON1 Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12-8PHELOCKCNTR/W0hInternal. Only to be used through TI provided API.
7-0PHELOCKTHRR/W0hInternal. Only to be used through TI provided API.

28.9.75 MOD0 Register (Offset = 140h) [Reset = 00000000h]

MOD0 is shown in Table 28-400.

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Internal. Only to be used through TI provided API.

Table 28-400 MOD0 Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12-11SCHEMER/W0hInternal. Only to be used through TI provided API.
10-8SYMSHPR/W0hInternal. Only to be used through TI provided API.
7-6CANPTHGAINR/W0hInternal. Only to be used through TI provided API.
5-4SHPGAINR/W0hInternal. Only to be used through TI provided API.
3-2INTPFACTR/W0hInternal. Only to be used through TI provided API.
1-0RESERVEDR0hReserved

28.9.76 MOD1 Register (Offset = 144h) [Reset = 00000000h]

MOD1 is shown in Table 28-401.

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Internal. Only to be used through TI provided API.

Table 28-401 MOD1 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0FOFFR/W0hInternal. Only to be used through TI provided API.

28.9.77 DTX0 Register (Offset = 148h) [Reset = 00000000h]

DTX0 is shown in Table 28-402.

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Internal. Only to be used through TI provided API.

Table 28-402 DTX0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP1R/W0hInternal. Only to be used through TI provided API.
7-0SHP0R/W0hInternal. Only to be used through TI provided API.

28.9.78 DTX1 Register (Offset = 14Ch) [Reset = 00000000h]

DTX1 is shown in Table 28-403.

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Internal. Only to be used through TI provided API.

Table 28-403 DTX1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP3R/W0hInternal. Only to be used through TI provided API.
7-0SHP2R/W0hInternal. Only to be used through TI provided API.

28.9.79 DTX2 Register (Offset = 150h) [Reset = 00000000h]

DTX2 is shown in Table 28-404.

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Internal. Only to be used through TI provided API.

Table 28-404 DTX2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP5R/W0hInternal. Only to be used through TI provided API.
7-0SHP4R/W0hInternal. Only to be used through TI provided API.

28.9.80 DTX3 Register (Offset = 154h) [Reset = 00000000h]

DTX3 is shown in Table 28-405.

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Internal. Only to be used through TI provided API.

Table 28-405 DTX3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP7R/W0hInternal. Only to be used through TI provided API.
7-0SHP6R/W0hInternal. Only to be used through TI provided API.

28.9.81 DTX4 Register (Offset = 158h) [Reset = 00000000h]

DTX4 is shown in Table 28-406.

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Internal. Only to be used through TI provided API.

Table 28-406 DTX4 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP9R/W0hInternal. Only to be used through TI provided API.
7-0SHP8R/W0hInternal. Only to be used through TI provided API.

28.9.82 DTX5 Register (Offset = 15Ch) [Reset = 00000000h]

DTX5 is shown in Table 28-407.

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Internal. Only to be used through TI provided API.

Table 28-407 DTX5 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP11R/W0hInternal. Only to be used through TI provided API.
7-0SHP10R/W0hInternal. Only to be used through TI provided API.

28.9.83 DTX6 Register (Offset = 160h) [Reset = 00000000h]

DTX6 is shown in Table 28-408.

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Internal. Only to be used through TI provided API.

Table 28-408 DTX6 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP13R/W0hInternal. Only to be used through TI provided API.
7-0SHP12R/W0hInternal. Only to be used through TI provided API.

28.9.84 DTX7 Register (Offset = 164h) [Reset = 00000000h]

DTX7 is shown in Table 28-409.

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Internal. Only to be used through TI provided API.

Table 28-409 DTX7 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP15R/W0hInternal. Only to be used through TI provided API.
7-0SHP14R/W0hInternal. Only to be used through TI provided API.

28.9.85 DTX8 Register (Offset = 168h) [Reset = 00000000h]

DTX8 is shown in Table 28-410.

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Internal. Only to be used through TI provided API.

Table 28-410 DTX8 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP17R/W0hInternal. Only to be used through TI provided API.
7-0SHP16R/W0hInternal. Only to be used through TI provided API.

28.9.86 DTX9 Register (Offset = 16Ch) [Reset = 00000000h]

DTX9 is shown in Table 28-411.

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Internal. Only to be used through TI provided API.

Table 28-411 DTX9 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP19R/W0hInternal. Only to be used through TI provided API.
7-0SHP18R/W0hInternal. Only to be used through TI provided API.

28.9.87 DTX10 Register (Offset = 170h) [Reset = 00000000h]

DTX10 is shown in Table 28-412.

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Internal. Only to be used through TI provided API.

Table 28-412 DTX10 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP21R/W0hInternal. Only to be used through TI provided API.
7-0SHP20R/W0hInternal. Only to be used through TI provided API.

28.9.88 DTX11 Register (Offset = 174h) [Reset = 00000000h]

DTX11 is shown in Table 28-413.

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Internal. Only to be used through TI provided API.

Table 28-413 DTX11 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8SHP23R/W0hInternal. Only to be used through TI provided API.
7-0SHP22R/W0hInternal. Only to be used through TI provided API.

28.9.89 PLLM0L Register (Offset = 178h) [Reset = 00000000h]

PLLM0L is shown in Table 28-414.

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Internal. Only to be used through TI provided API.

Table 28-414 PLLM0L Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-2VALLSBR/W0hInternal. Only to be used through TI provided API.
1-0SPARE0R/W0hInternal. Only to be used through TI provided API.

28.9.90 PLLM0H Register (Offset = 17Ch) [Reset = 00000000h]

PLLM0H is shown in Table 28-415.

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Internal. Only to be used through TI provided API.

Table 28-415 PLLM0H Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALMSBR/W0hInternal. Only to be used through TI provided API.

28.9.91 PLLM1L Register (Offset = 180h) [Reset = 00000000h]

PLLM1L is shown in Table 28-416.

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Internal. Only to be used through TI provided API.

Table 28-416 PLLM1L Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-2VALLSBR/W0hInternal. Only to be used through TI provided API.
1-0SPARE0R/W0hInternal. Only to be used through TI provided API.

28.9.92 PLLM1H Register (Offset = 184h) [Reset = 00000000h]

PLLM1H is shown in Table 28-417.

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Internal. Only to be used through TI provided API.

Table 28-417 PLLM1H Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALMSBR/W0hInternal. Only to be used through TI provided API.

28.9.93 CALMCRS Register (Offset = 188h) [Reset = 00000000h]

CALMCRS is shown in Table 28-418.

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Internal. Only to be used through TI provided API.

Table 28-418 CALMCRS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.94 CALMMID Register (Offset = 18Ch) [Reset = 00000000h]

CALMMID is shown in Table 28-419.

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Internal. Only to be used through TI provided API.

Table 28-419 CALMMID Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.95 REFDIV Register (Offset = 190h) [Reset = 00000000h]

REFDIV is shown in Table 28-420.

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Internal. Only to be used through TI provided API.

Table 28-420 REFDIV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0LOADR/W0hInternal. Only to be used through TI provided API.

28.9.96 DLOCTL0 Register (Offset = 198h) [Reset = 00000000h]

DLOCTL0 is shown in Table 28-421.

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Internal. Only to be used through TI provided API.

Table 28-421 DLOCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-8TDCSTOPR/W0hInternal. Only to be used through TI provided API.
7DTSTXTALR/W0hInternal. Only to be used through TI provided API.
6-4LOOPUPDR/W0hInternal. Only to be used through TI provided API.
3PH3R/W0hInternal. Only to be used through TI provided API.
2PH2R/W0hInternal. Only to be used through TI provided API.
1LOOPMODER/W0hInternal. Only to be used through TI provided API.
0RSTNR/W0hInternal. Only to be used through TI provided API.

28.9.97 DLOCTL1 Register (Offset = 1A0h) [Reset = 00000000h]

DLOCTL1 is shown in Table 28-422.

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Internal. Only to be used through TI provided API.

Table 28-422 DLOCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15DCOR/W0hInternal. Only to be used through TI provided API.
14-11RESERVEDR0hReserved
10LFSYNCATGRSHFTR/W0hInternal. Only to be used through TI provided API.
9LFSYNCATPEAKR/W0hInternal. Only to be used through TI provided API.
8PHEADJR/W0hInternal. Only to be used through TI provided API.
7FCDEMR/W0hInternal. Only to be used through TI provided API.
6DTSTCKVDR/W0hInternal. Only to be used through TI provided API.
5PHEDISCR/W0hInternal. Only to be used through TI provided API.
4PLLMONR/W0hInternal. Only to be used through TI provided API.
3IIRR/W0hInternal. Only to be used through TI provided API.
2MODR/W0hInternal. Only to be used through TI provided API.
1MODINITR/W0hInternal. Only to be used through TI provided API.
0MTDCRSTNR/W0hInternal. Only to be used through TI provided API.

28.9.98 DCOOVR0 Register (Offset = 1A8h) [Reset = 00000000h]

DCOOVR0 is shown in Table 28-423.

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Internal. Only to be used through TI provided API.

Table 28-423 DCOOVR0 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-8MIDCODER/W0hInternal. Only to be used through TI provided API.
7-4CRSCODER/W0hInternal. Only to be used through TI provided API.
3FINECTLR/W0hInternal. Only to be used through TI provided API.
2SDMICTLR/W0hInternal. Only to be used through TI provided API.
1MIDCTLR/W0hInternal. Only to be used through TI provided API.
0CRSCTLR/W0hInternal. Only to be used through TI provided API.

28.9.99 DCOOVR1 Register (Offset = 1ACh) [Reset = 00000000h]

DCOOVR1 is shown in Table 28-424.

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Internal. Only to be used through TI provided API.

Table 28-424 DCOOVR1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14-8FINECODER/W0hInternal. Only to be used through TI provided API.
7-0SDMICODER/W0hInternal. Only to be used through TI provided API.

28.9.100 DTST Register (Offset = 1B0h) [Reset = 00000000h]

DTST is shown in Table 28-425.

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Internal. Only to be used through TI provided API.

Table 28-425 DTST Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14-11SPARE11R/W0hInternal. Only to be used through TI provided API.
10-8VARTGLDLYR/W0hInternal. Only to be used through TI provided API.
7REFTGLDLYR/W0hInternal. Only to be used through TI provided API.
6TRNSEQR/W0hInternal. Only to be used through TI provided API.
5SPARE5R/W0hInternal. Only to be used through TI provided API.
4-0SIGR/W0hInternal. Only to be used through TI provided API.

28.9.101 DLOEV Register (Offset = 1B4h) [Reset = 00000000h]

DLOEV is shown in Table 28-426.

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Internal. Only to be used through TI provided API.

Table 28-426 DLOEV Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7LOCKR0hInternal. Only to be used through TI provided API.
6LOLR0hInternal. Only to be used through TI provided API.
5FCABVTHRR0hInternal. Only to be used through TI provided API.
4FCBLWTHRR0hInternal. Only to be used through TI provided API.
3-0STATER0hInternal. Only to be used through TI provided API.

28.9.102 DTSTRD Register (Offset = 1B8h) [Reset = 00000000h]

DTSTRD is shown in Table 28-427.

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Internal. Only to be used through TI provided API.

Table 28-427 DTSTRD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hInternal. Only to be used through TI provided API.

28.9.103 FDCOSPANLSB Register (Offset = 1C0h) [Reset = 00000000h]

FDCOSPANLSB is shown in Table 28-428.

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Internal. Only to be used through TI provided API.

Table 28-428 FDCOSPANLSB Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.104 FDCOSPANMSB Register (Offset = 1C4h) [Reset = 00000000h]

FDCOSPANMSB is shown in Table 28-429.

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Internal. Only to be used through TI provided API.

Table 28-429 FDCOSPANMSB Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0VALR0hInternal. Only to be used through TI provided API.

28.9.105 TDCCAL Register (Offset = 1C8h) [Reset = 00000000h]

TDCCAL is shown in Table 28-430.

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Internal. Only to be used through TI provided API.

Table 28-430 TDCCAL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.106 TDCCALLOW Register (Offset = 1CCh) [Reset = 00000000h]

TDCCALLOW is shown in Table 28-431.

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Internal. Only to be used through TI provided API.

Table 28-431 TDCCALLOW Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.107 TDCCALHIGH Register (Offset = 1D0h) [Reset = 00000000h]

TDCCALHIGH is shown in Table 28-432.

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Internal. Only to be used through TI provided API.

Table 28-432 TDCCALHIGH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.108 TDCODET Register (Offset = 1D4h) [Reset = 00000000h]

TDCODET is shown in Table 28-433.

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Internal. Only to be used through TI provided API.

Table 28-433 TDCODET Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0FLAGSR0hInternal. Only to be used through TI provided API.

28.9.109 CALRES Register (Offset = 1D8h) [Reset = 00000000h]

CALRES is shown in Table 28-434.

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Internal. Only to be used through TI provided API.

Table 28-434 CALRES Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-4MIDCODER0hInternal. Only to be used through TI provided API.
3-0CRSCODER0hInternal. Only to be used through TI provided API.

28.9.110 GPI Register (Offset = 1DCh) [Reset = 00000000h]

GPI is shown in Table 28-435.

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Internal. Only to be used through TI provided API.

Table 28-435 GPI Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7GPI7R0hInternal. Only to be used through TI provided API.
6GPI6R0hInternal. Only to be used through TI provided API.
5GPI5R0hInternal. Only to be used through TI provided API.
4GPI4R0hInternal. Only to be used through TI provided API.
3GPI3R0hInternal. Only to be used through TI provided API.
2GPI2R0hInternal. Only to be used through TI provided API.
1GPI1R0hInternal. Only to be used through TI provided API.
0GPI0R0hInternal. Only to be used through TI provided API.

28.9.111 MATHACCELIN Register (Offset = 1E0h) [Reset = 00000000h]

MATHACCELIN is shown in Table 28-436.

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Internal. Only to be used through TI provided API.

Table 28-436 MATHACCELIN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.112 LIN2LOGOUT Register (Offset = 1E4h) [Reset = 00000000h]

LIN2LOGOUT is shown in Table 28-437.

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Internal. Only to be used through TI provided API.

Table 28-437 LIN2LOGOUT Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-0LOGVALR0hInternal. Only to be used through TI provided API.

28.9.113 DIVBY3OUT Register (Offset = 1E8h) [Reset = 00000000h]

DIVBY3OUT is shown in Table 28-438.

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Internal. Only to be used through TI provided API.

Table 28-438 DIVBY3OUT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0DIV3R0hInternal. Only to be used through TI provided API.

28.9.114 TIMCTL Register (Offset = 1ECh) [Reset = 00000000h]

TIMCTL is shown in Table 28-439.

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Internal. Only to be used through TI provided API.

Table 28-439 TIMCTL Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-8CPTSRCR/W0hInternal. Only to be used through TI provided API.
7CPTCTLR/W0hInternal. Only to be used through TI provided API.
6-5CNTRSRCR/W0hInternal. Only to be used through TI provided API.
4CNTRCLRR/W0hInternal. Only to be used through TI provided API.
3CNTRCTLR/W0hInternal. Only to be used through TI provided API.
2-1TIMSRCR/W0hInternal. Only to be used through TI provided API.
0TIMCTLR/W0hInternal. Only to be used through TI provided API.

28.9.115 TIMINC Register (Offset = 1F0h) [Reset = 00000000h]

TIMINC is shown in Table 28-440.

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Internal. Only to be used through TI provided API.

Table 28-440 TIMINC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.116 TIMPER Register (Offset = 1F4h) [Reset = 00000000h]

TIMPER is shown in Table 28-441.

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Internal. Only to be used through TI provided API.

Table 28-441 TIMPER Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.117 TIMCNT Register (Offset = 1F8h) [Reset = 00000000h]

TIMCNT is shown in Table 28-442.

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Internal. Only to be used through TI provided API.

Table 28-442 TIMCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.118 TIMCAPT Register (Offset = 1FCh) [Reset = 00000000h]

TIMCAPT is shown in Table 28-443.

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Internal. Only to be used through TI provided API.

Table 28-443 TIMCAPT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALUER0hInternal. Only to be used through TI provided API.

28.9.119 TRCCTRL Register (Offset = 200h) [Reset = 00000000h]

TRCCTRL is shown in Table 28-444.

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Internal. Only to be used through TI provided API.

Table 28-444 TRCCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0SENDW0hInternal. Only to be used through TI provided API.

28.9.120 TRCSTAT Register (Offset = 204h) [Reset = 00000000h]

TRCSTAT is shown in Table 28-445.

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Internal. Only to be used through TI provided API.

Table 28-445 TRCSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0BUSYR0hInternal. Only to be used through TI provided API.

28.9.121 TRCCMD Register (Offset = 208h) [Reset = 00000000h]

TRCCMD is shown in Table 28-446.

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Internal. Only to be used through TI provided API.

Table 28-446 TRCCMD Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-8PARCNTR/W0hInternal. Only to be used through TI provided API.
7-0PKTHDRR/W0hInternal. Only to be used through TI provided API.

28.9.122 TRCPAR0 Register (Offset = 20Ch) [Reset = 00000000h]

TRCPAR0 is shown in Table 28-447.

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Internal. Only to be used through TI provided API.

Table 28-447 TRCPAR0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.123 TRCPAR1 Register (Offset = 210h) [Reset = 00000000h]

TRCPAR1 is shown in Table 28-448.

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Internal. Only to be used through TI provided API.

Table 28-448 TRCPAR1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.124 GPOCTL Register (Offset = 214h) [Reset = 00000000h]

GPOCTL is shown in Table 28-449.

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Internal. Only to be used through TI provided API.

Table 28-449 GPOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15SEL7R/W0hInternal. Only to be used through TI provided API.
14SEL6R/W0hInternal. Only to be used through TI provided API.
13SEL5R/W0hInternal. Only to be used through TI provided API.
12SEL4R/W0hInternal. Only to be used through TI provided API.
11SEL3R/W0hInternal. Only to be used through TI provided API.
10SEL2R/W0hInternal. Only to be used through TI provided API.
9SEL1R/W0hInternal. Only to be used through TI provided API.
8SEL0R/W0hInternal. Only to be used through TI provided API.
7GPO7R/W0hInternal. Only to be used through TI provided API.
6GPO6R/W0hInternal. Only to be used through TI provided API.
5GPO5R/W0hInternal. Only to be used through TI provided API.
4GPO4R/W0hInternal. Only to be used through TI provided API.
3GPO3R/W0hInternal. Only to be used through TI provided API.
2GPO2R/W0hInternal. Only to be used through TI provided API.
1GPO1R/W0hInternal. Only to be used through TI provided API.
0GPO0R/W0hInternal. Only to be used through TI provided API.

28.9.125 ANAISOCTL Register (Offset = 218h) [Reset = 00000000h]

ANAISOCTL is shown in Table 28-450.

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Internal. Only to be used through TI provided API.

Table 28-450 ANAISOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4ADCDIGRSTNR/W0hInternal. Only to be used through TI provided API.
3IFADC2SVTISOR/W1hInternal. Only to be used through TI provided API.
2DIV2IFADCISOR/W1hInternal. Only to be used through TI provided API.
1MTDC2SVTISOR/W1hInternal. Only to be used through TI provided API.
0DIV2MTDCISOR/W1hInternal. Only to be used through TI provided API.

28.9.126 DIVCTL Register (Offset = 21Ch) [Reset = 00000000h]

DIVCTL is shown in Table 28-451.

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Internal. Only to be used through TI provided API.

Table 28-451 DIVCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15DIV2PH180R/W0hInternal. Only to be used through TI provided API.
14DIV2PH0R/W0hInternal. Only to be used through TI provided API.
13DIV2PH270R/W0hInternal. Only to be used through TI provided API.
12DIV2PH90R/W0hInternal. Only to be used through TI provided API.
11SPARE11R/W0hInternal. Only to be used through TI provided API.
10S1G20DBMMUXR/W0hInternal. Only to be used through TI provided API.
9ADCDIVR/W0hInternal. Only to be used through TI provided API.
8ENSYNTHR/W0hInternal. Only to be used through TI provided API.
7TXPH18020DBMDIVR/W0hInternal. Only to be used through TI provided API.
6TXPH020DBMDIVR/W0hInternal. Only to be used through TI provided API.
5TXPH180DIVR/W0hInternal. Only to be used through TI provided API.
4TXPH0DIVR/W0hInternal. Only to be used through TI provided API.
3RXPH90DIVR/W0hInternal. Only to be used through TI provided API.
2RXPH0DIVR/W0hInternal. Only to be used through TI provided API.
1Spare1R/W0hInternal. Only to be used through TI provided API.
0ENR/W0hInternal. Only to be used through TI provided API.

28.9.127 RXCTRL Register (Offset = 220h) [Reset = 00000000h]

RXCTRL is shown in Table 28-452.

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Internal. Only to be used through TI provided API.

Table 28-452 RXCTRL Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12SPARER/W0hInternal. Only to be used through TI provided API.
11-9ATTNR/W0hInternal. Only to be used through TI provided API.
8-4IFAMPGCR/W0hInternal. Only to be used through TI provided API.
3-0LNAGAINR/W0hInternal. Only to be used through TI provided API.

28.9.128 MAGNACC0 Register (Offset = 224h) [Reset = 00000000h]

MAGNACC0 is shown in Table 28-453.

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Internal. Only to be used through TI provided API.

Table 28-453 MAGNACC0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.129 MAGNACC1 Register (Offset = 228h) [Reset = 00000000h]

MAGNACC1 is shown in Table 28-454.

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Internal. Only to be used through TI provided API.

Table 28-454 MAGNACC1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR0hInternal. Only to be used through TI provided API.

28.9.130 RSSI Register (Offset = 22Ch) [Reset = 00000000h]

RSSI is shown in Table 28-455.

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Internal. Only to be used through TI provided API.

Table 28-455 RSSI Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.131 RSSIMAX Register (Offset = 230h) [Reset = 00000000h]

RSSIMAX is shown in Table 28-456.

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Internal. Only to be used through TI provided API.

Table 28-456 RSSIMAX Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0VALR/W0hInternal. Only to be used through TI provided API.

28.9.132 RFGAIN Register (Offset = 234h) [Reset = 00000000h]

RFGAIN is shown in Table 28-457.

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Internal. Only to be used through TI provided API.

Table 28-457 RFGAIN Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0DBGAINR/W0hInternal. Only to be used through TI provided API.

28.9.133 IFADCSTAT Register (Offset = 238h) [Reset = 00000000h]

IFADCSTAT is shown in Table 28-458.

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Internal. Only to be used through TI provided API.

Table 28-458 IFADCSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RESERVEDR0hInternal. Only to be used through TI provided API.
6-2QUANTCALVALR0hInternal. Only to be used through TI provided API.
1QUANTCALDONER0hInternal. Only to be used through TI provided API.
0RESERVEDR0hInternal. Only to be used through TI provided API.

28.9.134 DIVSTA Register (Offset = 23Ch) [Reset = 00000000h]

DIVSTA is shown in Table 28-459.

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Internal. Only to be used through TI provided API.

Table 28-459 DIVSTA Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STATR0hInternal. Only to be used through TI provided API.

28.9.135 DIVIDENDL Register (Offset = 240h) [Reset = 00000000h]

DIVIDENDL is shown in Table 28-460.

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Internal. Only to be used through TI provided API.

Table 28-460 DIVIDENDL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALLSBW0hInternal. Only to be used through TI provided API.

28.9.136 DIVIDENDH Register (Offset = 244h) [Reset = 00000000h]

DIVIDENDH is shown in Table 28-461.

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Internal. Only to be used through TI provided API.

Table 28-461 DIVIDENDH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALMSBW0hInternal. Only to be used through TI provided API.

28.9.137 DIVISORL Register (Offset = 248h) [Reset = 00000000h]

DIVISORL is shown in Table 28-462.

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Internal. Only to be used through TI provided API.

Table 28-462 DIVISORL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALLSBR/W0hInternal. Only to be used through TI provided API.

28.9.138 DIVISORH Register (Offset = 24Ch) [Reset = 00000000h]

DIVISORH is shown in Table 28-463.

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Internal. Only to be used through TI provided API.

Table 28-463 DIVISORH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALMSBR/W0hInternal. Only to be used through TI provided API.

28.9.139 QUOTIENTL Register (Offset = 250h) [Reset = 00000000h]

QUOTIENTL is shown in Table 28-464.

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Internal. Only to be used through TI provided API.

Table 28-464 QUOTIENTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALLSBR0hInternal. Only to be used through TI provided API.

28.9.140 QUOTIENTH Register (Offset = 254h) [Reset = 00000000h]

QUOTIENTH is shown in Table 28-465.

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Internal. Only to be used through TI provided API.

Table 28-465 QUOTIENTH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALMSBR0hInternal. Only to be used through TI provided API.

28.9.141 PRODUCTL Register (Offset = 258h) [Reset = 00000000h]

PRODUCTL is shown in Table 28-466.

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Internal. Only to be used through TI provided API.

Table 28-466 PRODUCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALLSBR0hInternal. Only to be used through TI provided API.

28.9.142 PRODUCTH Register (Offset = 25Ch) [Reset = 00000000h]

PRODUCTH is shown in Table 28-467.

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Internal. Only to be used through TI provided API.

Table 28-467 PRODUCTH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALMSBR0hInternal. Only to be used through TI provided API.

28.9.143 MULTSTA Register (Offset = 260h) [Reset = 00000000h]

MULTSTA is shown in Table 28-468.

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Internal. Only to be used through TI provided API.

Table 28-468 MULTSTA Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STATR0hInternal. Only to be used through TI provided API.

28.9.144 MULTCFG Register (Offset = 268h) [Reset = 00000000h]

MULTCFG is shown in Table 28-469.

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Internal. Only to be used through TI provided API.

Table 28-469 MULTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0MODER/W0hInternal. Only to be used through TI provided API.

28.9.145 PA1 Register (Offset = 26Ch) [Reset = 00000000h]

PA1 is shown in Table 28-470.

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Internal. Only to be used through TI provided API.

Table 28-470 PA1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-13SPARE0R/W0hInternal. Only to be used through TI provided API.
12-11MODER/W0hInternal. Only to be used through TI provided API.
10-8GAINR/W0hInternal. Only to be used through TI provided API.
7-2IBR/W0hInternal. Only to be used through TI provided API.
1-0IBBOOSTR/W0hInternal. Only to be used through TI provided API.

28.9.146 PA2 Register (Offset = 270h) [Reset = 00000000h]

PA2 is shown in Table 28-471.

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Internal. Only to be used through TI provided API.

Table 28-471 PA2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-5SPARE5R/W0hInternal. Only to be used through TI provided API.
4-0TRIMR/W0hInternal. Only to be used through TI provided API.